From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 74ED04BE457; Mon, 12 Oct 2026 17:32:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791826378; cv=none; b=EB36LTDSTIr84GDZ8h6qsiSz8xe63gdJSZ+Eq9By//dhwZjaDjfWgpz25S6org8HdYic/RLCoY+mZaNGWb/sDyTq6WBQiodebOc2Ib3pTG67zFFonGvdrIf1AHEB7oblPh6PIBTKvsK9vey5sA48h6B/cYYxaGZLUJwjpdw82lk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791826378; c=relaxed/simple; bh=Ben9ds7l5snlJMg8NPMQQZULDqBGhQj1SfVWHLiwrlA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=O7FzunkPv36brVQZwB9yHmhwaelt9NfzyKy1PVmM31uX0P575H2RHGYLIXdW8iQOhM94Emg+GfhXu4TgGGKA94/aV2LnqxsbUhdHHi6pCdYhwGkxLxwNRUtnieIVmk0WghDFYSt0vua2cFUqLI2Hw0SF6qWBglZvFkJpMqsW+a4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=EIIuX59b; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="EIIuX59b" Received: by smtp.kernel.org (Postfix) with ESMTPS id 3BC38C2BCFD; Mon, 12 Oct 2026 17:32:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1791826378; bh=Ben9ds7l5snlJMg8NPMQQZULDqBGhQj1SfVWHLiwrlA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=EIIuX59bzzt1wIQ7KqG0rE1JlLqb50B8/qB4Hs2CUqVf5lLRrACGTOcJJKuLzzwJt 7VrEa9afCWi6BllLDIGl7AlYxFPGM8zJxsZTe9YY0grbPKFk1Q46bzFQUUkiHOfWGA IgmiOBuhv7qwqILLATbrKQg1DyedNl0GY6tSz6utUDW7vKmhfVRpzU4I8Wc6eh4h4p srKK3obCAemayA3akBIxHY9MN5GrVnFF6UY0Q8fD/tzRm49OtK7OAUsKyU6NgSo1XO n0huE6bsON2MkO2lGGfqstFpgEHW8wB8eHZG3Hx5V9sa8SmuAIkW2RrNb3EM2wDhpy FTM9ngvCtmLRA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 21CA7CA9EC5; Mon, 12 Oct 2026 17:32:58 +0000 (UTC) From: Fil Dunsky via B4 Relay Date: Mon, 12 Oct 2026 20:32:58 +0300 Subject: [PATCH 03/11] dt-bindings: gpio: Add Cortina Systems CS7542 GPIO controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261012-b4-cs75xx-s2-v1-3-8a7641b7b79c@gmail.com> References: <20261012-b4-cs75xx-s2-v1-0-8a7641b7b79c@gmail.com> In-Reply-To: <20261012-b4-cs75xx-s2-v1-0-8a7641b7b79c@gmail.com> To: Thomas Gleixner , Radu Rendec , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Bartosz Golaszewski , Andi Shyti , Wim Van Sebroeck , Guenter Roeck , Russell King , Arnd Bergmann , Krzysztof Kozlowski Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-i2c@vger.kernel.org, linux-watchdog@vger.kernel.org, Fil Dunsky X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1791826375; l=2368; i=filipp.dunsky@gmail.com; s=20260930; h=from:subject:message-id; bh=uz2ou1IT1ghc6GBy1z+YYFHHajTQ9VyMONdxfzPSdIk=; b=8+fbyqjLofqG9WBhmK3gaslEb9wRm4Pc5xw3UL1wayW/7eXxOp9epY3IB4OdC3VgYa5cymASk Oxp0F5tSARSCXp2/j+1xmBxbShTVxqPqFd0+4f2NQ2MHlJX6TOvnV+q X-Developer-Key: i=filipp.dunsky@gmail.com; a=ed25519; pk=JAYP8e2rJ54DHOmhNtXud8rl1igAaAXoOHxtJmVXI1g= X-Endpoint-Received: by B4 Relay for filipp.dunsky@gmail.com/20260930 with auth_id=1085 X-Original-From: Fil Dunsky Reply-To: filipp.dunsky@gmail.com From: Fil Dunsky The Cortina Systems CS75xx SoCs have five banks of 32 GPIO lines. Each pin is shared between a GPIO line and a peripheral function, selected by the bank's GPIO_MUX register in the global control block, which is described as the second register region of the bank. Signed-off-by: Fil Dunsky --- .../bindings/gpio/cortina,cs7542-gpio.yaml | 68 ++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/Documentation/devicetree/bindings/gpio/cortina,cs7542-gpio.yaml b/Documentation/devicetree/bindings/gpio/cortina,cs7542-gpio.yaml new file mode 100644 index 000000000..b54421d65 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/cortina,cs7542-gpio.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/cortina,cs7542-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cortina Systems CS7542 GPIO controller + +maintainers: + - Fil Dunsky + +description: + The Cortina Systems CS75xx (Goldengate G2) SoCs have five banks of 32 + GPIO lines, each with its own interrupt. Every pin is shared between a + GPIO line and a peripheral function; the choice is made per pin in the + GPIO_MUX register of the bank, which is part of the global control + block. + +properties: + compatible: + const: cortina,cs7542-gpio + + reg: + items: + - description: GPIO bank registers + - description: GPIO_MUX register of the bank + + interrupts: + maxItems: 1 + + gpio-controller: true + + "#gpio-cells": + const: 2 + + gpio-line-names: + maxItems: 32 + + gpio-reserved-ranges: true + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + +required: + - compatible + - reg + - interrupts + - gpio-controller + - "#gpio-cells" + - interrupt-controller + - "#interrupt-cells" + +additionalProperties: false + +examples: + - | + gpio@f00701f0 { + compatible = "cortina,cs7542-gpio"; + reg = <0xf00701f0 0x20>, <0xf0000020 0x4>; + interrupt-parent = <&intc>; + interrupts = <7>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; -- 2.53.0