From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 777144BE45A; Mon, 12 Oct 2026 17:32:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791826378; cv=none; b=WRi9ZppVbnDFK5JZ5oJW6LRCEMwDtoJVw2VnqirGLpkTk0F8RzoJbl3XUn+odnqut2b2I8mh3ubEZZtg+qjraoVpKEdcJl/tHr3blO0l1fVgQUZ13JZ8kc1P7SXHBQnd/Vf3WXgIC51mI/0qF92k3MHqQ7n2CNhKuJsYO7nqBTo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791826378; c=relaxed/simple; bh=GDQK5aQ3GQpRAuRY4DbNLUPBWTZvA6Ix98HJcg8/OUA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Q9G+yKsg35R22Luobv0bszdAUue8KQjGqq5y1RoIvHF3yjJ89ndFl8gDGIl2cMnR1FjKECAGcVO8RuYcZDWCFvKAyxesTL+36iaU2+JMIEjf+LdVYOr7fnGA2f4hMIz21Dxc2b2usQUhT7/aPcxta2E35zTfzIreYRTq3uxzVNI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=B2QoGLt8; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="B2QoGLt8" Received: by smtp.kernel.org (Postfix) with ESMTPS id 4CAA7C2BD01; Mon, 12 Oct 2026 17:32:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1791826378; bh=GDQK5aQ3GQpRAuRY4DbNLUPBWTZvA6Ix98HJcg8/OUA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=B2QoGLt83nGdu0FwWKuPirfQSm+atju0uFs7EFtVNAA/flwkup6LPQzsOtLnzgRNF 99TSW0pBRUEYdGNZ3ZdhwjWhVd77O6Nc4jUbXvsY2TFy0KW8i4qInRJgMfJxGHIDfJ om0EE1lFE/RGeP8ccepjxZv9J8LPB58zbUIrY5+FWNwRA4UJ3Nch2IU+bhW1AtUbCg K6iaiP/dH8oYHm3imjbhIIIvjQYka0RpslwhZ6+rZ5HJqgdTFKcFMwjI1AcaOkiGYZ /qANsh7T+cuOz11vWdsQkSWfiFWmNKo1l2bGem3Ibqgl8/gSKBUq5NBUfDogQ8PY25 SGa+tXjkLliig== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 367F7CA9EDF; Mon, 12 Oct 2026 17:32:58 +0000 (UTC) From: Fil Dunsky via B4 Relay Date: Mon, 12 Oct 2026 20:32:59 +0300 Subject: [PATCH 04/11] gpio: Add Cortina Systems CS75xx GPIO driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261012-b4-cs75xx-s2-v1-4-8a7641b7b79c@gmail.com> References: <20261012-b4-cs75xx-s2-v1-0-8a7641b7b79c@gmail.com> In-Reply-To: <20261012-b4-cs75xx-s2-v1-0-8a7641b7b79c@gmail.com> To: Thomas Gleixner , Radu Rendec , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Bartosz Golaszewski , Andi Shyti , Wim Van Sebroeck , Guenter Roeck , Russell King , Arnd Bergmann , Krzysztof Kozlowski Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-i2c@vger.kernel.org, linux-watchdog@vger.kernel.org, Fil Dunsky X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1791826375; l=11608; i=filipp.dunsky@gmail.com; s=20260930; h=from:subject:message-id; bh=ZwRTDWavLQSb0St+1TG7sYCqyjrb76jRDjSBduPk5qQ=; b=gkQ4/Ku85MGPuJhB7JjaaBx6mFCpeyyuWsqYqfFIP5CaRExq+KDV/wj6eEaVcDMiT68mFMB/M TIo2333Eb+WA7xewvWCjhqSR8ppkrlwgQj2ZbWnSf2jyGpC1EuyxPPL X-Developer-Key: i=filipp.dunsky@gmail.com; a=ed25519; pk=JAYP8e2rJ54DHOmhNtXud8rl1igAaAXoOHxtJmVXI1g= X-Endpoint-Received: by B4 Relay for filipp.dunsky@gmail.com/20260930 with auth_id=1085 X-Original-From: Fil Dunsky Reply-To: filipp.dunsky@gmail.com From: Fil Dunsky Add a driver for the GPIO banks of the Cortina Systems CS75xx SoCs. The data and direction registers are handled by gpio-mmio; each bank has its own interrupt with level and edge triggers, both edges are emulated by flipping the polarity. A pin only works as a GPIO when its bit in the bank's GPIO_MUX register is set. The driver sets it when a line is requested as a GPIO or as an interrupt and restores the value found at probe time when the line is released. Signed-off-by: Fil Dunsky --- drivers/gpio/Kconfig | 12 ++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-cs75xx.c | 332 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 345 insertions(+) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index dfdc9ee1a..6b9524f25 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -300,6 +300,18 @@ config GPIO_CLPS711X help Say yes here to support GPIO on CLPS711X SoCs. +config GPIO_CS75XX + tristate "Cortina Systems CS75xx GPIO support" + depends on ARCH_CORTINA_ACCESS || COMPILE_TEST + select GPIO_GENERIC + select GPIOLIB_IRQCHIP + help + Say yes here to support the GPIO banks of the Cortina Systems + CS75xx SoCs, including their interrupts. + + Requesting a line switches its pin from the peripheral function + to GPIO until the line is released. + config GPIO_DAVINCI tristate "TI Davinci/Keystone GPIO support" default y if ARCH_DAVINCI diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 88f748846..a38ad4331 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -59,6 +59,7 @@ obj-$(CONFIG_GPIO_CLPS711X) += gpio-clps711x.o obj-$(CONFIG_GPIO_SNPS_CREG) += gpio-creg-snps.o obj-$(CONFIG_GPIO_CROS_EC) += gpio-cros-ec.o obj-$(CONFIG_GPIO_CRYSTAL_COVE) += gpio-crystalcove.o +obj-$(CONFIG_GPIO_CS75XX) += gpio-cs75xx.o obj-$(CONFIG_GPIO_CS5535) += gpio-cs5535.o obj-$(CONFIG_GPIO_DA9052) += gpio-da9052.o obj-$(CONFIG_GPIO_DA9055) += gpio-da9055.o diff --git a/drivers/gpio/gpio-cs75xx.c b/drivers/gpio/gpio-cs75xx.c new file mode 100644 index 000000000..168af0e37 --- /dev/null +++ b/drivers/gpio/gpio-cs75xx.c @@ -0,0 +1,332 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Cortina Systems CS75xx GPIO controller + * + * Each bank has 32 lines with direction, data and interrupt registers. + * Whether a pin is driven by the GPIO bank or by its peripheral function + * (NAND, Ethernet, UART, ...) is selected by the bank's GPIO_MUX register + * in the global control block. A line is switched to GPIO when it is + * requested as a GPIO or as an interrupt and switched back to its initial + * setting when it is released. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define CS75XX_GPIO_CFG 0x00 /* 1: input, 0: output */ +#define CS75XX_GPIO_OUT 0x04 +#define CS75XX_GPIO_IN 0x08 +#define CS75XX_GPIO_LVL 0x0c /* 1: high level or rising edge */ +#define CS75XX_GPIO_EDGE 0x10 /* 1: edge, 0: level */ +#define CS75XX_GPIO_IE 0x14 +#define CS75XX_GPIO_INT 0x18 /* write 1 to clear */ + +struct cs75xx_gpio { + struct gpio_generic_chip chip; + void __iomem *base; + void __iomem *mux; + u32 mux_init; + u32 gpio_used; + u32 irq_used; + u32 both_edges; +}; + +/* Called with the chip lock held */ +static void cs75xx_gpio_update_mux(struct cs75xx_gpio *g, unsigned int offset) +{ + u32 mask = BIT(offset); + u32 val = readl(g->mux); + + if ((g->gpio_used | g->irq_used) & mask) + val |= mask; + else + val = (val & ~mask) | (g->mux_init & mask); + + writel(val, g->mux); +} + +static int cs75xx_gpio_request(struct gpio_chip *gc, unsigned int offset) +{ + struct cs75xx_gpio *g = gpiochip_get_data(gc); + + guard(gpio_generic_lock_irqsave)(&g->chip); + g->gpio_used |= BIT(offset); + cs75xx_gpio_update_mux(g, offset); + + return 0; +} + +static void cs75xx_gpio_free(struct gpio_chip *gc, unsigned int offset) +{ + struct cs75xx_gpio *g = gpiochip_get_data(gc); + + guard(gpio_generic_lock_irqsave)(&g->chip); + g->gpio_used &= ~BIT(offset); + cs75xx_gpio_update_mux(g, offset); +} + +static void cs75xx_gpio_irq_ack(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct cs75xx_gpio *g = gpiochip_get_data(gc); + + writel(BIT(irqd_to_hwirq(d)), g->base + CS75XX_GPIO_INT); +} + +static void cs75xx_gpio_irq_mask(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct cs75xx_gpio *g = gpiochip_get_data(gc); + irq_hw_number_t hwirq = irqd_to_hwirq(d); + + scoped_guard(gpio_generic_lock_irqsave, &g->chip) { + u32 ie = readl(g->base + CS75XX_GPIO_IE); + + writel(ie & ~BIT(hwirq), g->base + CS75XX_GPIO_IE); + } + + gpiochip_disable_irq(gc, hwirq); +} + +static void cs75xx_gpio_irq_unmask(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct cs75xx_gpio *g = gpiochip_get_data(gc); + irq_hw_number_t hwirq = irqd_to_hwirq(d); + u32 ie; + + gpiochip_enable_irq(gc, hwirq); + + guard(gpio_generic_lock_irqsave)(&g->chip); + /* + * The status of a level interrupt is latched while the line is + * asserted, also after the ack, so it may be stale by now. Clear it, + * it is set again right away if the line is still asserted. + */ + if (irqd_is_level_type(d)) + writel(BIT(hwirq), g->base + CS75XX_GPIO_INT); + ie = readl(g->base + CS75XX_GPIO_IE); + writel(ie | BIT(hwirq), g->base + CS75XX_GPIO_IE); +} + +/* Both edges are emulated by flipping the polarity on every interrupt */ +static void cs75xx_gpio_set_polarity(struct cs75xx_gpio *g, u32 mask) +{ + u32 lvl = readl(g->base + CS75XX_GPIO_LVL); + + if (readl(g->base + CS75XX_GPIO_IN) & mask) + lvl &= ~mask; + else + lvl |= mask; + + writel(lvl, g->base + CS75XX_GPIO_LVL); +} + +static int cs75xx_gpio_irq_set_type(struct irq_data *d, unsigned int type) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct cs75xx_gpio *g = gpiochip_get_data(gc); + u32 mask = BIT(irqd_to_hwirq(d)); + u32 lvl, edge; + + guard(gpio_generic_lock_irqsave)(&g->chip); + + lvl = readl(g->base + CS75XX_GPIO_LVL); + edge = readl(g->base + CS75XX_GPIO_EDGE); + g->both_edges &= ~mask; + + switch (type & IRQ_TYPE_SENSE_MASK) { + case IRQ_TYPE_LEVEL_LOW: + lvl &= ~mask; + edge &= ~mask; + break; + case IRQ_TYPE_LEVEL_HIGH: + lvl |= mask; + edge &= ~mask; + break; + case IRQ_TYPE_EDGE_FALLING: + lvl &= ~mask; + edge |= mask; + break; + case IRQ_TYPE_EDGE_RISING: + lvl |= mask; + edge |= mask; + break; + case IRQ_TYPE_EDGE_BOTH: + g->both_edges |= mask; + edge |= mask; + break; + default: + return -EINVAL; + } + + writel(lvl, g->base + CS75XX_GPIO_LVL); + writel(edge, g->base + CS75XX_GPIO_EDGE); + if (g->both_edges & mask) + cs75xx_gpio_set_polarity(g, mask); + + if (type & IRQ_TYPE_LEVEL_MASK) + irq_set_handler_locked(d, handle_level_irq); + else + irq_set_handler_locked(d, handle_edge_irq); + + return 0; +} + +static int cs75xx_gpio_irq_reqres(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct cs75xx_gpio *g = gpiochip_get_data(gc); + irq_hw_number_t hwirq = irqd_to_hwirq(d); + int ret; + + /* The boot loader may leave the line configured as an output */ + ret = gc->direction_input(gc, hwirq); + if (ret) + return ret; + + ret = gpiochip_reqres_irq(gc, hwirq); + if (ret) + return ret; + + guard(gpio_generic_lock_irqsave)(&g->chip); + g->irq_used |= BIT(hwirq); + cs75xx_gpio_update_mux(g, hwirq); + + return 0; +} + +static void cs75xx_gpio_irq_relres(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct cs75xx_gpio *g = gpiochip_get_data(gc); + irq_hw_number_t hwirq = irqd_to_hwirq(d); + + scoped_guard(gpio_generic_lock_irqsave, &g->chip) { + g->irq_used &= ~BIT(hwirq); + cs75xx_gpio_update_mux(g, hwirq); + } + + gpiochip_relres_irq(gc, hwirq); +} + +static const struct irq_chip cs75xx_gpio_irq_chip = { + .name = "cs75xx-gpio", + .irq_ack = cs75xx_gpio_irq_ack, + .irq_mask = cs75xx_gpio_irq_mask, + .irq_unmask = cs75xx_gpio_irq_unmask, + .irq_set_type = cs75xx_gpio_irq_set_type, + .irq_request_resources = cs75xx_gpio_irq_reqres, + .irq_release_resources = cs75xx_gpio_irq_relres, + .flags = IRQCHIP_IMMUTABLE | IRQCHIP_MASK_ON_SUSPEND, +}; + +static void cs75xx_gpio_irq_handler(struct irq_desc *desc) +{ + struct gpio_chip *gc = irq_desc_get_handler_data(desc); + struct cs75xx_gpio *g = gpiochip_get_data(gc); + struct irq_chip *chip = irq_desc_get_chip(desc); + unsigned long pending; + unsigned int offset; + + chained_irq_enter(chip, desc); + + pending = readl(g->base + CS75XX_GPIO_INT) & + readl(g->base + CS75XX_GPIO_IE); + + for_each_set_bit(offset, &pending, gc->ngpio) { + if (g->both_edges & BIT(offset)) { + guard(gpio_generic_lock)(&g->chip); + cs75xx_gpio_set_polarity(g, BIT(offset)); + } + generic_handle_domain_irq(gc->irq.domain, offset); + } + + chained_irq_exit(chip, desc); +} + +static int cs75xx_gpio_probe(struct platform_device *pdev) +{ + struct gpio_generic_chip_config config; + struct device *dev = &pdev->dev; + struct gpio_irq_chip *girq; + struct cs75xx_gpio *g; + int irq, ret; + + g = devm_kzalloc(dev, sizeof(*g), GFP_KERNEL); + if (!g) + return -ENOMEM; + + g->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(g->base)) + return PTR_ERR(g->base); + + g->mux = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(g->mux)) + return PTR_ERR(g->mux); + + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + g->mux_init = readl(g->mux); + + config = (struct gpio_generic_chip_config) { + .dev = dev, + .sz = 4, + .dat = g->base + CS75XX_GPIO_IN, + .set = g->base + CS75XX_GPIO_OUT, + .dirin = g->base + CS75XX_GPIO_CFG, + }; + + ret = gpio_generic_chip_init(&g->chip, &config); + if (ret) + return dev_err_probe(dev, ret, "unable to init generic GPIO\n"); + + g->chip.gc.request = cs75xx_gpio_request; + g->chip.gc.free = cs75xx_gpio_free; + g->chip.gc.owner = THIS_MODULE; + + /* Mask and clear all interrupts before the parent is set up */ + writel(0, g->base + CS75XX_GPIO_IE); + writel(~0, g->base + CS75XX_GPIO_INT); + + girq = &g->chip.gc.irq; + gpio_irq_chip_set_chip(girq, &cs75xx_gpio_irq_chip); + girq->parent_handler = cs75xx_gpio_irq_handler; + girq->num_parents = 1; + girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), + GFP_KERNEL); + if (!girq->parents) + return -ENOMEM; + girq->parents[0] = irq; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_bad_irq; + + return devm_gpiochip_add_data(dev, &g->chip.gc, g); +} + +static const struct of_device_id cs75xx_gpio_of_match[] = { + { .compatible = "cortina,cs7542-gpio" }, + { } +}; +MODULE_DEVICE_TABLE(of, cs75xx_gpio_of_match); + +static struct platform_driver cs75xx_gpio_driver = { + .probe = cs75xx_gpio_probe, + .driver = { + .name = "cs75xx-gpio", + .of_match_table = cs75xx_gpio_of_match, + }, +}; +module_platform_driver(cs75xx_gpio_driver); + +MODULE_DESCRIPTION("Cortina Systems CS75xx GPIO driver"); +MODULE_LICENSE("GPL"); -- 2.53.0