From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 67F14437107; Mon, 12 Oct 2026 06:58:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791788313; cv=none; b=lEq66GopgidJU9eo2Dlro9QEwTz9Pis6bmbAGv4xCLysTzwaKjc35XoQ4GZi3bjxHZ6ZZYx9wui1ydxvWeOSx25boL3+fUZf4qdVxdjtWQdg4ldSggWp8z4LyvaiC9rhsurmlvsGZ9rXz4xBTDtgIEmx1ACTAeQcO78UX5u9sCk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791788313; c=relaxed/simple; bh=kbzWEJG3RS0uRhAVKboubU+SQaTYUAE0pi1FzWvqMkI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=MsbshxUHdko1E9YSo+1AxRzhri/SYKv1PE3qIxKEt+pm/7evrmSQJkqibDhoJAfkHuSlGpcCsPfotIOIwraesNNDB7UtwZkyxWlL8fPXEvOIsglsRlyleHnhQLV61C5vsHeFOoyYEK50W2G7BQ1S3O+MdX7OtwLMh5/WLCvznmU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=BorEUdRz; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="BorEUdRz" Received: by smtp.kernel.org (Postfix) with ESMTPS id 23D6AC2BCFF; Mon, 12 Oct 2026 06:58:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1791788313; bh=kbzWEJG3RS0uRhAVKboubU+SQaTYUAE0pi1FzWvqMkI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=BorEUdRzsAfpipQCGj0yE1tRyA3OjoVf4cirn/OQGZK7CfeceCcFGHFv6Jz2oMjic owstXvxO/dNTGKoliCUFjAe19XL0+gyYVw+klxLW99U4AiPUPWAEx+7nBPT0oozhaV /gF69n/sCUEvXI+hc9Gmj4Na1V+0eXJsYVDD4jEXpEuJdj/4W/2KX3A6cO4JUDbIXp 3fis4R9KGH2hZh9r0nfbuCI2g6wfVRZD9lCpRgl3r6ygX2jRhrsXnZa0jeyXNoj7z+ clxRRav8Xqg7I7MKUTtFTHlD+yn5mFGmVYhx1b2whMIYE9fLXDfxgwJJwE8wVTfE7f tY53ek+9hVlPw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 09AF0CA9ED5; Mon, 12 Oct 2026 06:58:33 +0000 (UTC) From: Fil Dunsky via B4 Relay Date: Mon, 12 Oct 2026 09:58:33 +0300 Subject: [PATCH RFC v3 03/10] dt-bindings: arm: cpus: Add Cortina Systems CS7542 enable method Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261012-b4-cs75xx-v3-3-0e0d17a098cf@gmail.com> References: <20261012-b4-cs75xx-v3-0-0e0d17a098cf@gmail.com> In-Reply-To: <20261012-b4-cs75xx-v3-0-0e0d17a098cf@gmail.com> To: Arnd Bergmann , Linus Walleij , Krzysztof Kozlowski Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , Jiri Slaby , Russell King , Alexandre Belloni , Drew Fustini , Lorenzo Pieralisi , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, Jason Li , Fil Dunsky X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1791788310; l=1280; i=filipp.dunsky@gmail.com; s=20260930; h=from:subject:message-id; bh=zDmn+esXces7eieK+stPpF5FV5ebbgc0xe7in2CfHQ8=; b=KfHI9qnCfq7zCeyCyYma2HPx6TBdenZzEYtmFjFtsX6QRdEuh6M1ULY/y62HA2/+fQAPMi5oE c/LD7aeSVe5CL1W3GR+m09He6ZuyjgZQNHDoP2L8JEAPzUzlhOjajnU X-Developer-Key: i=filipp.dunsky@gmail.com; a=ed25519; pk=JAYP8e2rJ54DHOmhNtXud8rl1igAaAXoOHxtJmVXI1g= X-Endpoint-Received: by B4 Relay for filipp.dunsky@gmail.com/20260930 with auth_id=1085 X-Original-From: Fil Dunsky Reply-To: filipp.dunsky@gmail.com From: Fil Dunsky On the CS7542 the bootloader parks the secondary Cortex-A9 core in a loop that waits for an event and then jumps to the address found in a global software register. Add the "cortina,cs7542-smp" enable method for it and, as with the other release-address based methods, require cpu-release-addr to point at that register. Reviewed-by: Linus Walleij Signed-off-by: Fil Dunsky --- Documentation/devicetree/bindings/arm/cpus.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 96136b70d..7a394c500 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -269,6 +269,7 @@ properties: - brcm,bcm63138 - brcm,bcm-nsp-smp - brcm,brahma-b15 + - cortina,cs7542-smp - marvell,armada-375-smp - marvell,armada-380-smp - marvell,armada-390-smp @@ -484,6 +485,7 @@ allOf: enable-method: enum: - spin-table + - cortina,cs7542-smp - renesas,r9a06g032-smp required: - enable-method -- 2.53.0