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a=ed25519-sha256; t=1791829086; l=8671; i=kishore.batta@oss.qualcomm.com; s=20260206; h=from:subject:message-id; bh=ZtZ6u+DRu7HtGnSn8MYFTYGuqWBEm+LcrAFnqwamhXs=; b=6itkh64ThW6+pfLMUuaUqc9NPEi6VPZWJcO0Y1CuAsqnrXwtH3sJFh7mZMrw2y93zC8mfOIf3 53QEPLu6qPjA85xpzUM1pc99nRv1o7M4S7wjoHA9uHsx/PwzrlRHost X-Developer-Key: i=kishore.batta@oss.qualcomm.com; a=ed25519; pk=vJo8RvTf+HZpRLK2oOIljmbn9l3zFkibCGh+blaqZCw= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDEyMDA3MiBTYWx0ZWRfXzl85lrr5SQm6 4xETvkzb88Kc8IH2aZS+fizY7IBATGMsVRA962WvniKLSa8rTJqrlNkrb++GIndVDvNhv7LvKEr 997glMGyLNW2iD5+ohE33iZ0BDGKNge6f1mNNGdtlIRIACG3riyiGo2j1emXGlL0VXffIMSv+cN ardzqu3CgcSTboyRqFXYxnxk5rJBnil/jZjjd0bqQ48I3HCo3+/+gwYllMhUHJT2xZGiJhiQGVh r3/n+yDiPrYcX4AbbuUiix/CMZ4zYo2VL/UqUwaoXH17yeS3awycb+HZE4f0dUJeXQRww4ytWlf HzIq/fw05Wct7gp0VUOEcX3FAo8ycgo0w0BgUPUCyu/PZfqOhDxrxgm3VPmNJT7jYHuoY3Z1li6 RHUg7EvUtfJyj2YnLyKi9HuZPjPYFrem1rjvmXBSY4ENkSjYBc/MjZaVtJ9fmSXeyJsJ5M7iUR8 3ECDWIMXxfHhN6gH5ng== X-Proofpoint-GUID: 1s4QZb3Z7wbr3OwrUYLAqcWrWgOV5RLS X-Proofpoint-Spam-Info: AW1haW4tMjYxMDEyMDA3MiBTYWx0ZWRfXwuuHfsE/23h/ RMJA3LJXfLiKHRZ8f04rE7EW9Sc7LZuwDQoBIJfZ2grp4HO+4+3croEMeA5nsZLZjyREI4vWOQX 7n2IUWCJfAUgK9x2S3wHhF0rhImgFeI= X-Authority-Analysis: v=2.4 cv=ZcWIpcVA c=1 sm=1 tr=0 ts=6acd2474 cx=c_pps a=cFYjgdjTJScbgFmBucgdfQ==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=FaWmrOfgj8M-bvBoqZ0A:9 a=QEXdDO2ut3YA:10 a=scEy_gLbYbu1JhEsrz4S:22 X-Proofpoint-ORIG-GUID: 1s4QZb3Z7wbr3OwrUYLAqcWrWgOV5RLS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-12_05,2026-10-09_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 clxscore=1015 priorityscore=1501 suspectscore=0 spamscore=0 lowpriorityscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610080000 definitions=main-2610120072 The Sahara driver currently selects firmware image tables using scattered, device specific conditionals in the probe path. This makes the logic harder to follow, harder to extend for new devices, and spreads device knowledge across multiple code paths. Refactor firmware image table selection into a single, explicit probe time mechanism by introducing a controller provided firmware mapping table that captures device matching, Sahara image tables, firmware folder names, and streaming behaviour in one place. This centralizes device specific decisions in the controller driver, simplifies the Sahara probe logic, and removes ad-hoc conditionals while preserving existing behavior for all supported AIC devices. This is in preparation for adding QDU100 support. Signed-off-by: Kishore Batta --- drivers/accel/qaic/mhi_controller.c | 61 ++++++++++++++++++++++++++++ drivers/bus/mhi/host/clients/sahara/sahara.c | 60 +++++---------------------- include/linux/mhi.h | 17 ++++++++ 3 files changed, 88 insertions(+), 50 deletions(-) diff --git a/drivers/accel/qaic/mhi_controller.c b/drivers/accel/qaic/mhi_controller.c index 40e6d262ef217aad8ddff6f69a38388ef683e3ed..dd320739c07ad4a35b74446e32f0e8e64e847d16 100644 --- a/drivers/accel/qaic/mhi_controller.c +++ b/drivers/accel/qaic/mhi_controller.c @@ -20,6 +20,62 @@ static unsigned int mhi_timeout_ms = 2000; /* 2 sec default */ module_param(mhi_timeout_ms, uint, 0600); MODULE_PARM_DESC(mhi_timeout_ms, "MHI controller timeout value"); +static const char * const aic100_image_table[] = { + [1] = "qcom/aic100/fw1.bin", + [2] = "qcom/aic100/fw2.bin", + [4] = "qcom/aic100/fw4.bin", + [5] = "qcom/aic100/fw5.bin", + [6] = "qcom/aic100/fw6.bin", + [8] = "qcom/aic100/fw8.bin", + [9] = "qcom/aic100/fw9.bin", + [10] = "qcom/aic100/fw10.bin", +}; + +static const char * const aic200_image_table[] = { + [5] = "qcom/aic200/uefi.elf", + [12] = "qcom/aic200/aic200-nsp.bin", + [23] = "qcom/aic200/aop.mbn", + [32] = "qcom/aic200/tz.mbn", + [33] = "qcom/aic200/hypvm.mbn", + [38] = "qcom/aic200/xbl_config.elf", + [39] = "qcom/aic200/aic200_abl.elf", + [40] = "qcom/aic200/apdp.mbn", + [41] = "qcom/aic200/devcfg.mbn", + [42] = "qcom/aic200/sec.elf", + [43] = "qcom/aic200/aic200-hlos.elf", + [49] = "qcom/aic200/shrm.elf", + [50] = "qcom/aic200/cpucp.elf", + [51] = "qcom/aic200/aop_devcfg.mbn", + [54] = "qcom/aic200/qupv3fw.elf", + [57] = "qcom/aic200/cpucp_dtbs.elf", + [62] = "qcom/aic200/uefi_dtbs.elf", + [63] = "qcom/aic200/xbl_ac_config.mbn", + [64] = "qcom/aic200/tz_ac_config.mbn", + [65] = "qcom/aic200/hyp_ac_config.mbn", + [66] = "qcom/aic200/pdp.elf", + [67] = "qcom/aic200/pdp_cdb.elf", + [68] = "qcom/aic200/sdi.mbn", + [69] = "qcom/aic200/dcd.mbn", + [73] = "qcom/aic200/gearvm.mbn", + [74] = "qcom/aic200/sti.bin", + [76] = "qcom/aic200/tz_qti_config.mbn", + [78] = "qcom/aic200/pvs.bin", +}; + +static const struct mhi_sahara_fw_table aic100_sahara_fw = { + .image_table = aic100_image_table, + .table_size = ARRAY_SIZE(aic100_image_table), + .fw_folder = "aic100", + .non_streaming = true, +}; + +static const struct mhi_sahara_fw_table aic200_sahara_fw = { + .image_table = aic200_image_table, + .table_size = ARRAY_SIZE(aic200_image_table), + .fw_folder = "aic200", + .non_streaming = false, +}; + static const char *fw_image_paths[FAMILY_MAX] = { [FAMILY_AIC100] = "qcom/aic100/sbl.bin", [FAMILY_AIC200] = "qcom/aic200/sbl.bin", @@ -871,6 +927,11 @@ struct mhi_controller *qaic_mhi_register_controller(struct pci_dev *pci_dev, voi mhi_cntrl->name = "AIC100"; } + if (mhi_cntrl->name && !strcmp(mhi_cntrl->name, "AIC100")) + mhi_cntrl->sahara_fw = &aic100_sahara_fw; + else if (mhi_cntrl->name && !strcmp(mhi_cntrl->name, "AIC200")) + mhi_cntrl->sahara_fw = &aic200_sahara_fw; + /* use latest configured timeout */ mhi_config.timeout_ms = mhi_timeout_ms; ret = mhi_register_controller(mhi_cntrl, &mhi_config); diff --git a/drivers/bus/mhi/host/clients/sahara/sahara.c b/drivers/bus/mhi/host/clients/sahara/sahara.c index dc64beae06ada6915a506ed8f4ae4d71c03158bb..74bf57f02873e463d0c2cfdd2673237840169df2 100644 --- a/drivers/bus/mhi/host/clients/sahara/sahara.c +++ b/drivers/bus/mhi/host/clients/sahara/sahara.c @@ -179,48 +179,7 @@ struct sahara_context { u32 read_data_length; bool is_mem_dump_mode; bool non_streaming; -}; - -static const char * const aic100_image_table[] = { - [1] = "qcom/aic100/fw1.bin", - [2] = "qcom/aic100/fw2.bin", - [4] = "qcom/aic100/fw4.bin", - [5] = "qcom/aic100/fw5.bin", - [6] = "qcom/aic100/fw6.bin", - [8] = "qcom/aic100/fw8.bin", - [9] = "qcom/aic100/fw9.bin", - [10] = "qcom/aic100/fw10.bin", -}; - -static const char * const aic200_image_table[] = { - [5] = "qcom/aic200/uefi.elf", - [12] = "qcom/aic200/aic200-nsp.bin", - [23] = "qcom/aic200/aop.mbn", - [32] = "qcom/aic200/tz.mbn", - [33] = "qcom/aic200/hypvm.mbn", - [38] = "qcom/aic200/xbl_config.elf", - [39] = "qcom/aic200/aic200_abl.elf", - [40] = "qcom/aic200/apdp.mbn", - [41] = "qcom/aic200/devcfg.mbn", - [42] = "qcom/aic200/sec.elf", - [43] = "qcom/aic200/aic200-hlos.elf", - [49] = "qcom/aic200/shrm.elf", - [50] = "qcom/aic200/cpucp.elf", - [51] = "qcom/aic200/aop_devcfg.mbn", - [54] = "qcom/aic200/qupv3fw.elf", - [57] = "qcom/aic200/cpucp_dtbs.elf", - [62] = "qcom/aic200/uefi_dtbs.elf", - [63] = "qcom/aic200/xbl_ac_config.mbn", - [64] = "qcom/aic200/tz_ac_config.mbn", - [65] = "qcom/aic200/hyp_ac_config.mbn", - [66] = "qcom/aic200/pdp.elf", - [67] = "qcom/aic200/pdp_cdb.elf", - [68] = "qcom/aic200/sdi.mbn", - [69] = "qcom/aic200/dcd.mbn", - [73] = "qcom/aic200/gearvm.mbn", - [74] = "qcom/aic200/sti.bin", - [76] = "qcom/aic200/tz_qti_config.mbn", - [78] = "qcom/aic200/pvs.bin", + const char *fw_folder; }; static bool is_streaming(struct sahara_context *context) @@ -796,6 +755,7 @@ static void sahara_read_data_processing(struct work_struct *work) static int sahara_mhi_probe(struct mhi_device *mhi_dev, const struct mhi_device_id *id) { + const struct mhi_sahara_fw_table *sahara_fw; struct sahara_context *context; int ret; int i; @@ -808,14 +768,14 @@ static int sahara_mhi_probe(struct mhi_device *mhi_dev, const struct mhi_device_ if (!context->rx) return -ENOMEM; - if (!strcmp(mhi_dev->mhi_cntrl->name, "AIC200")) { - context->image_table = aic200_image_table; - context->table_size = ARRAY_SIZE(aic200_image_table); - } else { - context->image_table = aic100_image_table; - context->table_size = ARRAY_SIZE(aic100_image_table); - context->non_streaming = true; - } + sahara_fw = mhi_dev->mhi_cntrl->sahara_fw; + if (!sahara_fw || !sahara_fw->image_table || !sahara_fw->table_size) + return -ENODEV; + + context->image_table = sahara_fw->image_table; + context->table_size = sahara_fw->table_size; + context->non_streaming = sahara_fw->non_streaming; + context->fw_folder = sahara_fw->fw_folder; /* * There are two firmware implementations for READ_DATA handling. diff --git a/include/linux/mhi.h b/include/linux/mhi.h index 65e8a397cc50b89d045a242aa1164ea7fb8c9696..e1d12e8c1eb80945be6a6d0a5896d92ac221ab81 100644 --- a/include/linux/mhi.h +++ b/include/linux/mhi.h @@ -252,6 +252,21 @@ struct mhi_channel_config { bool wake_capable; }; +/** + * struct mhi_sahara_fw_table - Controller provided sahara firmware mapping + * @image_table: Sparse array indexed by Sahara image ID + * @table_size: Size of @image_table + * @fw_folder: Firmware folder name. + * @non_streaming: Streaming feature support (optional) + * + */ +struct mhi_sahara_fw_table { + const char *const *image_table; + u32 table_size; + const char *fw_folder; + bool non_streaming; +}; + /** * struct mhi_event_config - Event ring configuration structure for controller * @num_elements: The number of elements that can be queued to this ring @@ -381,6 +396,7 @@ struct mhi_controller_config { * @no_m3: Device doesn't support M3 state * @irq_flags: irq flags passed to request_irq (optional) * @mru: the default MRU for the MHI device + * @sahara_fw: Sahara firmware mapping * * Fields marked as (required) need to be populated by the controller driver * before calling mhi_register_controller(). For the fields marked as (optional) @@ -467,6 +483,7 @@ struct mhi_controller { bool no_m3; unsigned long irq_flags; u32 mru; + const struct mhi_sahara_fw_table *sahara_fw; }; /** -- 2.34.1