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Mon, 12 Oct 2026 06:52:14 -0700 (PDT) Received: from [127.0.1.1] ([82.71.135.85]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48db94e3519sm21355523f8f.16.2026.10.12.06.52.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Oct 2026 06:52:13 -0700 (PDT) From: William Bright Date: Mon, 12 Oct 2026 14:52:01 +0100 Subject: [PATCH v2 2/3] media: qcom: camss: Add the SM8550 CSI TPGs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261012-sm8550-camss-tpg-v2-2-06dbbe36ecd2@imd-tec.com> References: <20261012-sm8550-camss-tpg-v2-0-06dbbe36ecd2@imd-tec.com> In-Reply-To: <20261012-sm8550-camss-tpg-v2-0-06dbbe36ecd2@imd-tec.com> To: Bryan O'Donoghue , Vladimir Zapolskiy , Loic Poulain , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Depeng Shao , Bjorn Andersson , Konrad Dybcio Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, William Bright X-Mailer: b4 0.15.2 The SM8550 TPGs are hardware version 2.1.0, the same as x1e80100, so describe them with the gen1 TPG ops. Assisted-by: Claude:claude-opus-5-5 Reviewed-by: Bryan O'Donoghue Signed-off-by: William Bright --- drivers/media/platform/qcom/camss/camss.c | 50 +++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c index 5128dae79103..70f327484503 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -3553,6 +3553,54 @@ static const struct camss_subdev_resources csid_res_8550[] = { } }; +static const struct camss_subdev_resources tpg_res_8550[] = { + /* TPG0 */ + { + .regulators = {}, + .clock = { "cpas_ahb", "csiphy_rx" }, + .clock_rate = { + { 0 }, + { 400000000 }, + }, + .reg = { "csitpg0" }, + .tpg = { + .lane_cnt = 4, + .formats = &tpg_formats_gen1, + .hw_ops = &tpg_ops_gen1 + } + }, + /* TPG1 */ + { + .regulators = {}, + .clock = { "cpas_ahb", "csiphy_rx" }, + .clock_rate = { + { 0 }, + { 400000000 }, + }, + .reg = { "csitpg1" }, + .tpg = { + .lane_cnt = 4, + .formats = &tpg_formats_gen1, + .hw_ops = &tpg_ops_gen1 + } + }, + /* TPG2 */ + { + .regulators = {}, + .clock = { "cpas_ahb", "csiphy_rx" }, + .clock_rate = { + { 0 }, + { 400000000 }, + }, + .reg = { "csitpg2" }, + .tpg = { + .lane_cnt = 4, + .formats = &tpg_formats_gen1, + .hw_ops = &tpg_ops_gen1 + } + }, +}; + static const struct camss_subdev_resources vfe_res_8550[] = { /* VFE0 */ { @@ -7245,12 +7293,14 @@ static const struct camss_resources sm8550_resources = { .legacy_phy = true, .csiphy_res = csiphy_res_8550, .csid_res = csid_res_8550, + .tpg_res = tpg_res_8550, .vfe_res = vfe_res_8550, .csid_wrapper_res = &csid_wrapper_res_sm8550, .icc_res = icc_res_sm8550, .icc_path_num = ARRAY_SIZE(icc_res_sm8550), .csiphy_num = ARRAY_SIZE(csiphy_res_8550), .csid_num = ARRAY_SIZE(csid_res_8550), + .tpg_num = ARRAY_SIZE(tpg_res_8550), .vfe_num = ARRAY_SIZE(vfe_res_8550), }; -- 2.43.0