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Sun, 11 Oct 2026 22:23:59 -0700 (PDT) Received: from localhost (2620:10d:c0a8:fe::f072) by mail.thefacebook.com (2620:10d:c0a9:6f::237c) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.49; Mon, 12 Oct 2026 05:23:59 +0000 From: Amir Ayupov To: James Clark CC: Leo Yan , Suzuki K Poulose , Mike Leach , Alexander Shishkin , Jonathan Corbet , Shuah Khan , Randy Dunlap , , , , Subject: Re: [PATCH 1/2] coresight: etm4x: Report whether the PMU counts external output 1 Date: Sun, 11 Oct 2026 22:23:36 -0700 Message-ID: <20261012052353.3071404-1-aaupov@fb.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDEyMDAyMSBTYWx0ZWRfX2p496gn2iHED 9AjIqS+8Xvz0DLZzDjM6qCdEfFNZ8bZK5/qKRJUjZYik+XjBtvR6e2nPwX/v8CUJqQWIBj5N1p4 nBdwDs86JQBZBGw++7x0b/tGQCh/CKZ7fW2Z5Xgy9x3NgvYLO7ZO8iicIhMjMMCRRL/t48uTHQf sYkeT9+3TOK9TyqqWxLEebk0TrxXeLhqiqimZoalu5BxNd6mW7o200pzlNBx/HM4nPiRxRH9OQO A8WFbuAY6+cgy3mGuZRwKYFRBCUyvLQh/Qb66+oc5Vy8Skvq5Gj2SYDgaZ2C1II8T86tKzkxYW0 /h/+HvF5JiWcRj13wdvstH67EAbra9/UxlncoSVDJurWiEz3P2xz5EosBfnRdCTcSKAYo5AlYYW o2j10pVcgWQlYusbGxHSSpE2ofPCRYiYfO41+cjb/yj/fo22iCdZlz//A6P6exJ936VJbBe2lvs 7LzzrsVQOMa0gENft9Q== X-Proofpoint-GUID: y-fQXgSeMPHpEK_FzXDUsk6HJPoggu-g X-Proofpoint-ORIG-GUID: y-fQXgSeMPHpEK_FzXDUsk6HJPoggu-g X-Authority-Analysis: v=2.4 cv=Vom2kO2n c=1 sm=1 tr=0 ts=6acc6eef cx=c_pps a=MfjaFnPeirRr97d5FC5oHw==:117 a=MfjaFnPeirRr97d5FC5oHw==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=VkNPw1HP01LnGYTKEx00:22 a=7x6HtfJdh03M6CCDgxCd:22 a=xtH7KyWI9dI7BmFOsl-x:22 a=NEAV23lmAAAA:8 a=KKAkSRfTAAAA:8 a=3ApLgukL6kD-7lwlGNAA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Spam-Info: AW1haW4tMjYxMDEyMDAyMSBTYWx0ZWRfX13TlHVK96Dgk a7bE6bshGp/PAA0EibnWer4EDSrjiOb3tQ4/8stC8mBB/WLWBnYeZOu4W8nUOhyG6wqLklsvHpj WdDxWBJ6W7lhb+tunzzoXDFwH2aae2o= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-12_02,2026-10-09_01,2025-10-01_01 On Thu, 8 Oct 2026 09:38:52 +0100 James Clark wrote: Hi James, Please see answers inline: > > > On 07/10/2026 17:24, Leo Yan wrote: > > Hi Amir, > > > > Thanks for the patch. I have a few initial comments below. We may have > > further feedback after our internal review. > > > > On Wed, Sep 30, 2026 at 11:37:43PM -0700, Amir Ayupov wrote: > > > > [...] > > > >> #define CS_CFG_MATCH_CLASS_SRC_ALL 0x0001 /* match any source */ > >> #define CS_CFG_MATCH_CLASS_SRC_ETM4 0x0002 /* match any ETMv4 device */ > >> +/* ETM external output 1 is countable by the PMU as TRCEXTOUT1 */ > >> +#define CS_CFG_MATCH_CAP_PMU_EXTOUT1 0x0004 > > > > Do we need to tie this capability to TRCEXTOUT1? For example, Neoverse > > V2 exposes TRCEXTOUT0 through TRCEXTOUT3 as PMU events. > > > > Shouldn't we also use TRCEXTOUT0 instead of 1? Isn't 1 for devices that > have two external outputs, but some devices might only have 1 output so > only have TRCEXTOUT0? > IIUC we can't because output 0 is driven by event 0, which stops tracing: CoreSight Base System Architecture, RMHKBV (second bullet) > For at least one of the events implemented in the trace unit, when this event occurs, any trace buffer which > captures trace from this trace unit must be able to detect the event has occurred, and must be able to use this > event to stop trace capture. One of the following mechanisms must be used: > • Use of the trigger trace source ID value 0x7D as defined in [12], and use of the ATB Trigger Enable > function in the trace unit. > • Use of a dedicated mechanism when Event 0 occurs in the trace unit. > >> /* flags defining device instance matching - used in config match desc data. */ > >> #define CS_CFG_MATCH_INST_ANY 0x80000000 /* any instance of a class */ > >> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c > >> index e1a59b4345052..2847d2d7f7bed 100644 > >> --- a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c > >> +++ b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c > >> @@ -174,9 +174,14 @@ static int etm4_cfg_load_feature(struct coresight_device *csdev, > >> > >> int etm4_cscfg_register(struct coresight_device *csdev) > >> { > >> + struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); > >> struct cscfg_csdev_feat_ops ops; > >> + u32 match_flags = CS_CFG_ETM4_MATCH_FLAGS; > >> > >> ops.load_feat = &etm4_cfg_load_feature; > >> > >> - return cscfg_register_csdev(csdev, CS_CFG_ETM4_MATCH_FLAGS, &ops); > >> + if (drvdata->pmu_extout1) > >> + match_flags |= CS_CFG_MATCH_CAP_PMU_EXTOUT1; > >> + > >> + return cscfg_register_csdev(csdev, match_flags, &ops); > > > > The current matching logic succeeds if a device and feature share any > > flag bit. If the feature sets both CS_CFG_MATCH_CLASS_SRC_ETM4 and > > CS_CFG_MATCH_CAP_PMU_EXTOUT1, it will still load on an ETM4 device that > > lacks the capability. > > > > Could we check the capability separately when loading the feature, > > perhaps in cscfg_load_feat_csdev(), and skip it on unsupported devices? > > > >> +static bool etm4_pmu_has_extout1(struct etmv4_drvdata *drvdata) > >> +{ > >> + int pmuver = read_pmuver(); > >> + > >> + if (!is_midr_in_range_list(etm4_pmu_extout1_cpus)) > >> + return false; > > > > Based on specific CPU variant, we should already have identified > > TRCEXTOUT has supported. > > > > So either we only base on MIDR list or we can figure out a reliable > > way to detect the feature dynamically. > > > > At least with ETE the ARM says: > > D4.6.12 External Outputs > > SRBKWBThe TRCIDR0.NUMEVENT field shows how many ETEEvents are > for the particular implementation > > 0x4011, TRCEXTOUT1, Trace unit external output 1 > > > D14 PMU Event Descriptions > > The counter counts each event signaled by the trace unit on external > event 1. > > It is IMPLEMENTATION DEFINED whether this event is available as an > external input to the ETE. > > PMCEID0_EL0[49] reads as 1 if this event is implemented and 0 > otherwise. > > The number of outputs and the PMU event are both discoverable. It > specifically says that only the external input is implementation > defined, implying that if it's available it's always connected as an output. > > We could leave the MIDR list to only support errata when the external > output isn't connected to the PMU event. > > > I searched for TRCEXTOUT in errata notices and couldn't find any, so I'm dropping the list in v2. Feel free to add it in the future. > >> + > >> + /* PMCEID0_EL0[63:32] describe events 0x4000-0x401f from PMUv3p1 */ > >> + if (!pmuv3_implemented(pmuver) || pmuver < ID_AA64DFR0_EL1_PMUVer_V3P1) > >> + return false; > >> + if (!(read_pmceid0() & BIT_ULL(32 + ARMV8_PMUV3_PERFCTR_TRCEXTOUT1 - > >> + ARMV8_PMUV3_EXT_COMMON_EVENT_BASE))) > >> + return false; > >> + > >> + /* nr_event is TRCIDR0.NUMEVENT, the number of events minus one */ > >> + return drvdata->nr_event >= 1; > >> +} > > > > [...] > > > >> @@ -1116,6 +1116,13 @@ int cscfg_csdev_enable_active_config(struct coresight_device *csdev, > >> > >> if (err) > >> cscfg_config_desc_put(config_desc); > >> + } else { > >> + /* > >> + * The configuration is active but was not loaded on this > >> + * device, for example because the device lacks a capability > >> + * its features require. Fail rather than trace without it. > >> + */ > >> + err = -EINVAL; > >> } > > > > This fixes a pre-existing issue. It is worther to put it in a separate > > patch with fixes tag: > > > > An early return would also avoid the normal enable path's indentation: > > > > if (!config_csdev_active) > > return -EINVAL; > > > > err = cscfg_csdev_enable_config(config_csdev_active, preset); > > ... > > > > Thanks, > > Leo Sent using hkml (https://github.com/sjp38/hackermail)