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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2e8422da9b1sm39071745ad.66.2026.10.11.23.30.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Oct 2026 23:30:29 -0700 (PDT) From: Joey Lu To: sboyd@kernel.org Cc: ychuang3@nuvoton.com, schung@nuvoton.com, yclu4@nuvoton.com, arnd@arndb.de, bmasney+clk@redhat.com, jbrunet+clk@baylibre.com, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Joey Lu Subject: [PATCH 1/3] clk: nuvoton: ma35d1: fix parent lookup for clk_parent_data entries Date: Mon, 12 Oct 2026 14:30:18 +0800 Message-ID: <20261012063020.3331443-2-a0987203069@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261012063020.3331443-1-a0987203069@gmail.com> References: <20261012063020.3331443-1-a0987203069@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The parent tables were converted to struct clk_parent_data with only .fw_name set, for example { .fw_name = "hxt" }. The clock controller node has a single "clocks" entry for the external crystal and no "clock-names", so a firmware lookup by name can never succeed. The clk core falls back to a global name lookup only when .name is set, so these parents are never resolved. As a result sysclk1_mux and everything below it (hclk*, pclk*, and the peripheral dividers and gates) stay orphans with a rate of 0, and clk_set_rate() on any of their consumers returns early without programming the hardware. Set .name as well as .fw_name on every entry so the lookup falls back to the globally registered clock of that name. .fw_name is kept so the tables still work if clock-names is ever added to the binding. Fixes: f50a000b4219 ("clk: nuvoton: Use clk_parent_data instead of string for parent clock") Signed-off-by: Joey Lu --- drivers/clk/nuvoton/clk-ma35d1.c | 260 +++++++++++++++---------------- 1 file changed, 130 insertions(+), 130 deletions(-) diff --git a/drivers/clk/nuvoton/clk-ma35d1.c b/drivers/clk/nuvoton/clk-ma35d1.c index 9f65d0623517a..09e6ceeb2c556 100644 --- a/drivers/clk/nuvoton/clk-ma35d1.c +++ b/drivers/clk/nuvoton/clk-ma35d1.c @@ -63,298 +63,298 @@ static DEFINE_SPINLOCK(ma35d1_lock); #define PLL_MODE_SS 2 static const struct clk_parent_data ca35clk_sel_clks[] = { - { .fw_name = "hxt", }, - { .fw_name = "capll", }, - { .fw_name = "ddrpll", }, + { .fw_name = "hxt", .name = "hxt", }, + { .fw_name = "capll", .name = "capll", }, + { .fw_name = "ddrpll", .name = "ddrpll", }, }; static const struct clk_parent_data sysclk0_sel_clks[] = { - { .fw_name = "epll_div2", }, - { .fw_name = "syspll", }, + { .fw_name = "epll_div2", .name = "epll_div2", }, + { .fw_name = "syspll", .name = "syspll", }, }; static const struct clk_parent_data sysclk1_sel_clks[] = { - { .fw_name = "hxt", }, - { .fw_name = "syspll", }, + { .fw_name = "hxt", .name = "hxt", }, + { .fw_name = "syspll", .name = "syspll", }, }; static const struct clk_parent_data axiclk_sel_clks[] = { - { .fw_name = "capll_div2", }, - { .fw_name = "capll_div4", }, + { .fw_name = "capll_div2", .name = "capll_div2", }, + { .fw_name = "capll_div4", .name = "capll_div4", }, }; static const struct clk_parent_data ccap_sel_clks[] = { - { .fw_name = "hxt", }, - { .fw_name = "vpll", }, - { .fw_name = "apll", }, - { .fw_name = "syspll", }, + { .fw_name = "hxt", .name = "hxt", }, + { .fw_name = "vpll", .name = "vpll", }, + { .fw_name = "apll", .name = "apll", }, + { .fw_name = "syspll", .name = "syspll", }, }; static const struct clk_parent_data sdh_sel_clks[] = { - { .fw_name = "syspll", }, - { .fw_name = "apll", }, + { .fw_name = "syspll", .name = "syspll", }, + { .fw_name = "apll", .name = "apll", }, }; static const struct clk_parent_data dcu_sel_clks[] = { - { .fw_name = "epll_div2", }, - { .fw_name = "syspll", }, + { .fw_name = "epll_div2", .name = "epll_div2", }, + { .fw_name = "syspll", .name = "syspll", }, }; static const struct clk_parent_data gfx_sel_clks[] = { - { .fw_name = "epll", }, - { .fw_name = "syspll", }, + { .fw_name = "epll", .name = "epll", }, + { .fw_name = "syspll", .name = "syspll", }, }; static const struct clk_parent_data dbg_sel_clks[] = { - { .fw_name = "hirc", }, - { .fw_name = "syspll", }, + { .fw_name = "hirc", .name = "hirc", }, + { .fw_name = "syspll", .name = "syspll", }, }; static const struct clk_parent_data timer0_sel_clks[] = { - { .fw_name = "hxt", }, - { .fw_name = "lxt", }, - { .fw_name = "pclk0", }, + { .fw_name = "hxt", .name = "hxt", }, + { .fw_name = "lxt", .name = "lxt", }, + { .fw_name = "pclk0", .name = "pclk0", }, { .index = -1, }, { .index = -1, }, - { .fw_name = "lirc", }, + { .fw_name = "lirc", .name = "lirc", }, { .index = -1, }, - { .fw_name = "hirc", }, + { .fw_name = "hirc", .name = "hirc", }, }; static const struct clk_parent_data timer1_sel_clks[] = { - { .fw_name = "hxt", }, - { .fw_name = "lxt", }, - { .fw_name = "pclk0", }, + { .fw_name = "hxt", .name = "hxt", }, + { .fw_name = "lxt", .name = "lxt", }, + { .fw_name = "pclk0", .name = "pclk0", }, { .index = -1, }, { .index = -1, }, - { .fw_name = "lirc", }, + { .fw_name = "lirc", .name = "lirc", }, { .index = -1, }, - { .fw_name = "hirc", }, + { .fw_name = "hirc", .name = "hirc", }, }; static const struct clk_parent_data timer2_sel_clks[] = { - { .fw_name = "hxt", }, - { .fw_name = "lxt", }, - { .fw_name = "pclk1", }, + { .fw_name = "hxt", .name = "hxt", }, + { .fw_name = "lxt", .name = "lxt", }, + { .fw_name = "pclk1", .name = "pclk1", }, { .index = -1, }, { .index = -1, }, - { .fw_name = "lirc", }, + { .fw_name = "lirc", .name = "lirc", }, { .index = -1, }, - { .fw_name = "hirc", }, + { .fw_name = "hirc", .name = "hirc", }, }; static const struct clk_parent_data timer3_sel_clks[] = { - { .fw_name = "hxt", }, - { .fw_name = "lxt", }, - { .fw_name = "pclk1", }, + { .fw_name = "hxt", .name = "hxt", }, + { .fw_name = "lxt", .name = "lxt", }, + { .fw_name = "pclk1", .name = "pclk1", }, { .index = -1, }, { .index = -1, }, - { .fw_name = "lirc", }, + { .fw_name = "lirc", .name = "lirc", }, { .index = -1, }, - { .fw_name = "hirc", }, + { .fw_name = "hirc", .name = "hirc", }, }; static const struct clk_parent_data timer4_sel_clks[] = { - { .fw_name = "hxt", }, - { .fw_name = "lxt", }, - { .fw_name = "pclk2", }, + { .fw_name = "hxt", .name = "hxt", }, + { .fw_name = "lxt", .name = "lxt", }, + { .fw_name = "pclk2", .name = "pclk2", }, { .index = -1, }, { .index = -1, }, - { .fw_name = "lirc", }, + { .fw_name = "lirc", .name = "lirc", }, { .index = -1, }, - { .fw_name = "hirc", }, + { .fw_name = "hirc", .name = "hirc", }, }; static const struct clk_parent_data timer5_sel_clks[] = { - { .fw_name = "hxt", }, - { .fw_name = "lxt", }, - { .fw_name = "pclk2", }, + { .fw_name = "hxt", .name = "hxt", }, + { .fw_name = "lxt", .name = "lxt", }, + { .fw_name = "pclk2", .name = "pclk2", }, { .index = -1, }, { .index = -1, }, - { .fw_name = "lirc", }, + { .fw_name = "lirc", .name = "lirc", }, { .index = -1, }, - { .fw_name = "hirc", }, + { .fw_name = "hirc", .name = "hirc", }, }; static const struct clk_parent_data timer6_sel_clks[] = { - { .fw_name = "hxt", }, - { .fw_name = "lxt", }, - { .fw_name = "pclk0", }, + { .fw_name = "hxt", .name = "hxt", }, + { .fw_name = "lxt", .name = "lxt", }, + { .fw_name = "pclk0", .name = "pclk0", }, { .index = -1, }, { .index = -1, }, - { .fw_name = "lirc", }, + { .fw_name = "lirc", .name = "lirc", }, { .index = -1, }, - { .fw_name = "hirc", }, + { .fw_name = "hirc", .name = "hirc", }, }; static const struct clk_parent_data timer7_sel_clks[] = { - { .fw_name = "hxt", }, - { .fw_name = "lxt", }, - { .fw_name = "pclk0", }, + { .fw_name = "hxt", .name = "hxt", }, + { .fw_name = "lxt", .name = "lxt", }, + { .fw_name = "pclk0", .name = "pclk0", }, { .index = -1, }, { .index = -1, }, - { .fw_name = "lirc", }, + { .fw_name = "lirc", .name = "lirc", }, { .index = -1, }, - { .fw_name = "hirc", }, + { .fw_name = "hirc", .name = "hirc", }, }; static const struct clk_parent_data timer8_sel_clks[] = { - { .fw_name = "hxt", }, - { .fw_name = "lxt", }, - { .fw_name = "pclk1", }, + { .fw_name = "hxt", .name = "hxt", }, + { .fw_name = "lxt", .name = "lxt", }, + { .fw_name = "pclk1", .name = "pclk1", }, { .index = -1, }, { .index = -1, }, - { .fw_name = "lirc", }, + { .fw_name = "lirc", .name = "lirc", }, { .index = -1, }, - { .fw_name = "hirc", }, + { .fw_name = "hirc", .name = "hirc", }, }; static const struct clk_parent_data timer9_sel_clks[] = { - { .fw_name = "hxt", }, - { .fw_name = "lxt", }, - { .fw_name = "pclk1", }, + { .fw_name = "hxt", .name = "hxt", }, + { .fw_name = "lxt", .name = "lxt", }, + { .fw_name = "pclk1", .name = "pclk1", }, { .index = -1, }, { .index = -1, }, - { .fw_name = "lirc", }, + { .fw_name = "lirc", .name = "lirc", }, { .index = -1, }, - { .fw_name = "hirc", }, + { .fw_name = "hirc", .name = "hirc", }, }; static const struct clk_parent_data timer10_sel_clks[] = { - { .fw_name = "hxt", }, - { .fw_name = "lxt", }, - { .fw_name = "pclk2", }, + { .fw_name = "hxt", .name = "hxt", }, + { .fw_name = "lxt", .name = "lxt", }, + { .fw_name = "pclk2", .name = "pclk2", }, { .index = -1, }, { .index = -1, }, - { .fw_name = "lirc", }, + { .fw_name = "lirc", .name = "lirc", }, { .index = -1, }, - { .fw_name = "hirc", }, + { .fw_name = "hirc", .name = "hirc", }, }; static const struct clk_parent_data timer11_sel_clks[] = { - { .fw_name = "hxt", }, - { .fw_name = "lxt", }, - { .fw_name = "pclk2", }, + { .fw_name = "hxt", .name = "hxt", }, + { .fw_name = "lxt", .name = "lxt", }, + { .fw_name = "pclk2", .name = "pclk2", }, { .index = -1, }, { .index = -1, }, - { .fw_name = "lirc", }, + { .fw_name = "lirc", .name = "lirc", }, { .index = -1, }, - { .fw_name = "hirc", }, + { .fw_name = "hirc", .name = "hirc", }, }; static const struct clk_parent_data uart_sel_clks[] = { - { .fw_name = "hxt", }, - { .fw_name = "sysclk1_div2", }, + { .fw_name = "hxt", .name = "hxt", }, + { .fw_name = "sysclk1_div2", .name = "sysclk1_div2", }, }; static const struct clk_parent_data wdt0_sel_clks[] = { { .index = -1, }, - { .fw_name = "lxt", }, - { .fw_name = "pclk3_div4096", }, - { .fw_name = "lirc", }, + { .fw_name = "lxt", .name = "lxt", }, + { .fw_name = "pclk3_div4096", .name = "pclk3_div4096", }, + { .fw_name = "lirc", .name = "lirc", }, }; static const struct clk_parent_data wdt1_sel_clks[] = { { .index = -1, }, - { .fw_name = "lxt", }, - { .fw_name = "pclk3_div4096", }, - { .fw_name = "lirc", }, + { .fw_name = "lxt", .name = "lxt", }, + { .fw_name = "pclk3_div4096", .name = "pclk3_div4096", }, + { .fw_name = "lirc", .name = "lirc", }, }; static const struct clk_parent_data wdt2_sel_clks[] = { { .index = -1, }, - { .fw_name = "lxt", }, - { .fw_name = "pclk4_div4096", }, - { .fw_name = "lirc", }, + { .fw_name = "lxt", .name = "lxt", }, + { .fw_name = "pclk4_div4096", .name = "pclk4_div4096", }, + { .fw_name = "lirc", .name = "lirc", }, }; static const struct clk_parent_data wwdt0_sel_clks[] = { { .index = -1, }, { .index = -1, }, - { .fw_name = "pclk3_div4096", }, - { .fw_name = "lirc", }, + { .fw_name = "pclk3_div4096", .name = "pclk3_div4096", }, + { .fw_name = "lirc", .name = "lirc", }, }; static const struct clk_parent_data wwdt1_sel_clks[] = { { .index = -1, }, { .index = -1, }, - { .fw_name = "pclk3_div4096", }, - { .fw_name = "lirc", }, + { .fw_name = "pclk3_div4096", .name = "pclk3_div4096", }, + { .fw_name = "lirc", .name = "lirc", }, }; static const struct clk_parent_data wwdt2_sel_clks[] = { { .index = -1, }, { .index = -1, }, - { .fw_name = "pclk4_div4096", }, - { .fw_name = "lirc", }, + { .fw_name = "pclk4_div4096", .name = "pclk4_div4096", }, + { .fw_name = "lirc", .name = "lirc", }, }; static const struct clk_parent_data spi0_sel_clks[] = { - { .fw_name = "pclk1", }, - { .fw_name = "apll", }, + { .fw_name = "pclk1", .name = "pclk1", }, + { .fw_name = "apll", .name = "apll", }, }; static const struct clk_parent_data spi1_sel_clks[] = { - { .fw_name = "pclk2", }, - { .fw_name = "apll", }, + { .fw_name = "pclk2", .name = "pclk2", }, + { .fw_name = "apll", .name = "apll", }, }; static const struct clk_parent_data spi2_sel_clks[] = { - { .fw_name = "pclk1", }, - { .fw_name = "apll", }, + { .fw_name = "pclk1", .name = "pclk1", }, + { .fw_name = "apll", .name = "apll", }, }; static const struct clk_parent_data spi3_sel_clks[] = { - { .fw_name = "pclk2", }, - { .fw_name = "apll", }, + { .fw_name = "pclk2", .name = "pclk2", }, + { .fw_name = "apll", .name = "apll", }, }; static const struct clk_parent_data qspi0_sel_clks[] = { - { .fw_name = "pclk0", }, - { .fw_name = "apll", }, + { .fw_name = "pclk0", .name = "pclk0", }, + { .fw_name = "apll", .name = "apll", }, }; static const struct clk_parent_data qspi1_sel_clks[] = { - { .fw_name = "pclk0", }, - { .fw_name = "apll", }, + { .fw_name = "pclk0", .name = "pclk0", }, + { .fw_name = "apll", .name = "apll", }, }; static const struct clk_parent_data i2s0_sel_clks[] = { - { .fw_name = "apll", }, - { .fw_name = "sysclk1_div2", }, + { .fw_name = "apll", .name = "apll", }, + { .fw_name = "sysclk1_div2", .name = "sysclk1_div2", }, }; static const struct clk_parent_data i2s1_sel_clks[] = { - { .fw_name = "apll", }, - { .fw_name = "sysclk1_div2", }, + { .fw_name = "apll", .name = "apll", }, + { .fw_name = "sysclk1_div2", .name = "sysclk1_div2", }, }; static const struct clk_parent_data can_sel_clks[] = { - { .fw_name = "apll", }, - { .fw_name = "vpll", }, + { .fw_name = "apll", .name = "apll", }, + { .fw_name = "vpll", .name = "vpll", }, }; static const struct clk_parent_data cko_sel_clks[] = { - { .fw_name = "hxt", }, - { .fw_name = "lxt", }, - { .fw_name = "hirc", }, - { .fw_name = "lirc", }, - { .fw_name = "capll_div4", }, - { .fw_name = "syspll", }, - { .fw_name = "ddrpll", }, - { .fw_name = "epll_div2", }, - { .fw_name = "apll", }, - { .fw_name = "vpll", }, + { .fw_name = "hxt", .name = "hxt", }, + { .fw_name = "lxt", .name = "lxt", }, + { .fw_name = "hirc", .name = "hirc", }, + { .fw_name = "lirc", .name = "lirc", }, + { .fw_name = "capll_div4", .name = "capll_div4", }, + { .fw_name = "syspll", .name = "syspll", }, + { .fw_name = "ddrpll", .name = "ddrpll", }, + { .fw_name = "epll_div2", .name = "epll_div2", }, + { .fw_name = "apll", .name = "apll", }, + { .fw_name = "vpll", .name = "vpll", }, }; static const struct clk_parent_data smc_sel_clks[] = { - { .fw_name = "hxt", }, - { .fw_name = "pclk4", }, + { .fw_name = "hxt", .name = "hxt", }, + { .fw_name = "pclk4", .name = "pclk4", }, }; static const struct clk_parent_data kpi_sel_clks[] = { - { .fw_name = "hxt", }, - { .fw_name = "lxt", }, + { .fw_name = "hxt", .name = "hxt", }, + { .fw_name = "lxt", .name = "lxt", }, }; static const struct clk_div_table ip_div_table[] = { -- 2.43.0