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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2e8422da9b1sm39071745ad.66.2026.10.11.23.30.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Oct 2026 23:30:33 -0700 (PDT) From: Joey Lu To: sboyd@kernel.org Cc: ychuang3@nuvoton.com, schung@nuvoton.com, yclu4@nuvoton.com, arnd@arndb.de, bmasney+clk@redhat.com, jbrunet+clk@baylibre.com, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Joey Lu Subject: [PATCH 2/3] clk: nuvoton: ma35d1: use the generic divider for the ADC clock Date: Mon, 12 Oct 2026 14:30:19 +0800 Message-ID: <20261012063020.3331443-3-a0987203069@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261012063020.3331443-1-a0987203069@gmail.com> References: <20261012063020.3331443-1-a0987203069@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The ADC clock divider implements rate = parent_rate / (2 * (N + 1)), which is what the generic clk divider already provides with CLK_DIVIDER_EVEN_INTEGERS. Use it with CLK_DIVIDER_ROUND_CLOSEST, as the dedicated driver did, instead of a private clk_ops implementation. This also keeps the rate request propagation handled by divider_determine_rate(). The dedicated driver additionally OR'd a caller-supplied mask bit into the divider register on every set_rate(). Its only caller passed a bitmask (0x1ffff) rather than a bit index, which made BIT() shift by an out-of-range amount, and nothing requires an extra bit to be forced, so that behavior is not carried over. Signed-off-by: Joey Lu --- drivers/clk/nuvoton/clk-ma35d1.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/clk/nuvoton/clk-ma35d1.c b/drivers/clk/nuvoton/clk-ma35d1.c index 09e6ceeb2c556..523493e42e38c 100644 --- a/drivers/clk/nuvoton/clk-ma35d1.c +++ b/drivers/clk/nuvoton/clk-ma35d1.c @@ -1014,10 +1014,11 @@ static int ma35d1_clocks_probe(struct platform_device *pdev) hws[QEI2_GATE] = ma35d1_clk_gate(dev, "qei2_gate", "pclk1", clk_base + REG_CLK_APBCLK2, 14); - hws[ADC_DIV] = ma35d1_reg_adc_clkdiv(dev, "adc_div", hws[PCLK0], - &ma35d1_lock, 0, - clk_base + REG_CLK_CLKDIV4, - 4, 17, 0x1ffff); + hws[ADC_DIV] = devm_clk_hw_register_divider_parent_hw(dev, "adc_div", hws[PCLK0], 0, + clk_base + REG_CLK_CLKDIV4, 4, 17, + CLK_DIVIDER_EVEN_INTEGERS | + CLK_DIVIDER_ROUND_CLOSEST, + &ma35d1_lock); hws[ADC_GATE] = ma35d1_clk_gate(dev, "adc_gate", "adc_div", clk_base + REG_CLK_APBCLK2, 24); -- 2.43.0