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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2e8422da9b1sm39071745ad.66.2026.10.11.23.30.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Oct 2026 23:30:39 -0700 (PDT) From: Joey Lu To: sboyd@kernel.org Cc: ychuang3@nuvoton.com, schung@nuvoton.com, yclu4@nuvoton.com, arnd@arndb.de, bmasney+clk@redhat.com, jbrunet+clk@baylibre.com, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Joey Lu Subject: [PATCH 3/3] clk: nuvoton: ma35d1: remove the unused ADC divider driver Date: Mon, 12 Oct 2026 14:30:20 +0800 Message-ID: <20261012063020.3331443-4-a0987203069@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261012063020.3331443-1-a0987203069@gmail.com> References: <20261012063020.3331443-1-a0987203069@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The ADC divider is now registered with the generic clk divider, so clk-ma35d1-divider.c and its ma35d1_reg_adc_clkdiv() prototype have no users. Remove them, including the divider table it built with one entry per possible divider value. Signed-off-by: Joey Lu --- drivers/clk/nuvoton/Makefile | 1 - drivers/clk/nuvoton/clk-ma35d1-divider.c | 133 ----------------------- drivers/clk/nuvoton/clk-ma35d1.h | 5 - 3 files changed, 139 deletions(-) delete mode 100644 drivers/clk/nuvoton/clk-ma35d1-divider.c diff --git a/drivers/clk/nuvoton/Makefile b/drivers/clk/nuvoton/Makefile index c3c59dd9f2aaa..3d95466e69b9c 100644 --- a/drivers/clk/nuvoton/Makefile +++ b/drivers/clk/nuvoton/Makefile @@ -1,4 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_CLK_MA35D1) += clk-ma35d1.o -obj-$(CONFIG_CLK_MA35D1) += clk-ma35d1-divider.o obj-$(CONFIG_CLK_MA35D1) += clk-ma35d1-pll.o diff --git a/drivers/clk/nuvoton/clk-ma35d1-divider.c b/drivers/clk/nuvoton/clk-ma35d1-divider.c deleted file mode 100644 index e992e7c303419..0000000000000 --- a/drivers/clk/nuvoton/clk-ma35d1-divider.c +++ /dev/null @@ -1,133 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2023 Nuvoton Technology Corp. - * Author: Chi-Fang Li - */ - -#include -#include -#include -#include - -#include "clk-ma35d1.h" - -struct ma35d1_adc_clk_div { - struct clk_hw hw; - void __iomem *reg; - u8 shift; - u8 width; - u32 mask; - const struct clk_div_table *table; - /* protects concurrent access to clock divider registers */ - spinlock_t *lock; -}; - -static inline struct ma35d1_adc_clk_div *to_ma35d1_adc_clk_div(struct clk_hw *_hw) -{ - return container_of(_hw, struct ma35d1_adc_clk_div, hw); -} - -static unsigned long ma35d1_clkdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) -{ - unsigned int val; - struct ma35d1_adc_clk_div *dclk = to_ma35d1_adc_clk_div(hw); - - val = readl_relaxed(dclk->reg) >> dclk->shift; - val &= clk_div_mask(dclk->width); - val += 1; - return divider_recalc_rate(hw, parent_rate, val, dclk->table, - CLK_DIVIDER_ROUND_CLOSEST, dclk->width); -} - -static int ma35d1_clkdiv_determine_rate(struct clk_hw *hw, - struct clk_rate_request *req) -{ - struct ma35d1_adc_clk_div *dclk = to_ma35d1_adc_clk_div(hw); - - return divider_determine_rate(hw, req, dclk->table, dclk->width, - CLK_DIVIDER_ROUND_CLOSEST); -} - -static int ma35d1_clkdiv_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) -{ - int value; - unsigned long flags = 0; - u32 data; - struct ma35d1_adc_clk_div *dclk = to_ma35d1_adc_clk_div(hw); - - value = divider_get_val(rate, parent_rate, dclk->table, - dclk->width, CLK_DIVIDER_ROUND_CLOSEST); - - spin_lock_irqsave(dclk->lock, flags); - - data = readl_relaxed(dclk->reg); - data &= ~(clk_div_mask(dclk->width) << dclk->shift); - data |= (value - 1) << dclk->shift; - data |= dclk->mask; - writel_relaxed(data, dclk->reg); - - spin_unlock_irqrestore(dclk->lock, flags); - return 0; -} - -static const struct clk_ops ma35d1_adc_clkdiv_ops = { - .recalc_rate = ma35d1_clkdiv_recalc_rate, - .determine_rate = ma35d1_clkdiv_determine_rate, - .set_rate = ma35d1_clkdiv_set_rate, -}; - -struct clk_hw *ma35d1_reg_adc_clkdiv(struct device *dev, const char *name, - struct clk_hw *parent_hw, spinlock_t *lock, - unsigned long flags, void __iomem *reg, - u8 shift, u8 width, u32 mask_bit) -{ - struct ma35d1_adc_clk_div *div; - struct clk_init_data init; - struct clk_div_table *table; - struct clk_parent_data pdata = { .index = 0 }; - u32 max_div, min_div; - struct clk_hw *hw; - int ret; - int i; - - div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); - if (!div) - return ERR_PTR(-ENOMEM); - - max_div = clk_div_mask(width) + 1; - min_div = 1; - - table = devm_kcalloc(dev, max_div + 1, sizeof(*table), GFP_KERNEL); - if (!table) - return ERR_PTR(-ENOMEM); - - for (i = 0; i < max_div; i++) { - table[i].val = min_div + i; - table[i].div = 2 * table[i].val; - } - table[max_div].val = 0; - table[max_div].div = 0; - - memset(&init, 0, sizeof(init)); - init.name = name; - init.ops = &ma35d1_adc_clkdiv_ops; - init.flags |= flags; - pdata.hw = parent_hw; - init.parent_data = &pdata; - init.num_parents = 1; - - div->reg = reg; - div->shift = shift; - div->width = width; - div->mask = mask_bit ? BIT(mask_bit) : 0; - div->lock = lock; - div->hw.init = &init; - div->table = table; - - hw = &div->hw; - ret = devm_clk_hw_register(dev, hw); - if (ret) - return ERR_PTR(ret); - return hw; -} -EXPORT_SYMBOL_GPL(ma35d1_reg_adc_clkdiv); diff --git a/drivers/clk/nuvoton/clk-ma35d1.h b/drivers/clk/nuvoton/clk-ma35d1.h index 3adee440f60a3..06300511987ae 100644 --- a/drivers/clk/nuvoton/clk-ma35d1.h +++ b/drivers/clk/nuvoton/clk-ma35d1.h @@ -10,9 +10,4 @@ struct clk_hw *ma35d1_reg_clk_pll(struct device *dev, u32 id, u8 u8mode, const char *name, struct clk_hw *parent_hw, void __iomem *base); -struct clk_hw *ma35d1_reg_adc_clkdiv(struct device *dev, const char *name, - struct clk_hw *parent_hw, spinlock_t *lock, - unsigned long flags, void __iomem *reg, - u8 shift, u8 width, u32 mask_bit); - #endif /* __DRV_CLK_NUVOTON_MA35D1_H */ -- 2.43.0