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From: genevieve.chan@altera.com
To: dinguyen@kernel.org, robh@kernel.org, krzk+dt@kernel.org,
	conor+dt@kernel.org
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH v4 0/2] arm64: dts: socfpga: agilex: add SoCDK multi-QSPI board
Date: Mon, 12 Oct 2026 15:48:43 +0800	[thread overview]
Message-ID: <20261012074845.18039-1-genevieve.chan@altera.com> (raw)

From: Genevieve Chan <genevieve.chan@altera.com>

The Agilex SoCDK is populated with a single QSPI flash by default. A
multi-QSPI daughter board can be fitted in its place. That board connects
four Micron MT25QU02G devices (256 MiB each, 1 GiB total) to the HPS
QSPI controller on chip selects 0-3. Each device carries one partition
covering the whole flash, and is described in quad mode at 25 MHz, as
the four devices share the clock and data lines.

This is a board-level population difference, in the same way the
existing SoCDK eMMC and NAND variants differ from the default SoCDK.
The HPS is the Agilex SoC, later marketed as Agilex 7 F-Series. The
programming model is unchanged, so the board falls back to
"intel,socfpga-agilex" and does not add an F-Series SoC compatible.
Agilex 7 M-Series is a different device and already has its own
fallback.

Patch 1 documents that compatible next to the other Agilex SoCDK
boards. Patch 2 adds socfpga_agilex_socdk_multiqspi.dts. UART,
Ethernet, USB, SDMMC, LEDs and the watchdog match the SoCDK; the QSPI
node is the difference.

Changes in v4:
- Give the partitions on flash@1-3 unique labels so that they do not
  share an MTD name with flash@0 (Dinh, Sashiko). flash@0 keeps
  "Boot and fpga data", which U-Boot's RSU code looks up by name.
- Explain in the patch 2 commit message why the flashes run at 25 MHz
  rather than the 100 MHz used on the SoCDK (Dinh).

Changes in v3:
- Rebase onto the socfpga for-next branch, which moved the SoCFPGA
  device trees to arch/arm64/boot/dts/altera/. The new DTS is added
  there.
- Reword the subject of patch 2 to avoid repeating "Agilex" (Dinh).
- Add Conor's Acked-by to patch 1.

Changes in v2:
- Rename the compatible, DTS filename and model, dropping "agilex7f".
- State in the binding patch why the fallback is "intel,socfpga-agilex".
- Describe the daughter card instead of restating the diff.

Genevieve Chan (2):
  dt-bindings: arm: altera: add Agilex SoCDK multi-QSPI board
  arm64: dts: socfpga: agilex: add SoCDK multi-QSPI board

 .../devicetree/bindings/arm/altera.yaml       |   1 +
 arch/arm64/boot/dts/altera/Makefile           |   1 +
 .../altera/socfpga_agilex_socdk_multiqspi.dts | 213 ++++++++++++++++++
 3 files changed, 215 insertions(+)
 create mode 100644 arch/arm64/boot/dts/altera/socfpga_agilex_socdk_multiqspi.dts


base-commit: fd26798a69439d6693a1f83b0763031b306cfb4f
-- 
2.43.7


             reply	other threads:[~2026-10-12  7:48 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-12  7:48 genevieve.chan [this message]
2026-10-12  7:48 ` [PATCH v4 1/2] dt-bindings: arm: altera: add Agilex " genevieve.chan
2026-10-12  7:48 ` [PATCH v4 2/2] arm64: dts: socfpga: agilex: add " genevieve.chan
2026-10-26 14:04 ` [PATCH v4 0/2] " Dinh Nguyen

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