mirror of https://lore.kernel.org/lkml/
 help / color / mirror / Atom feed
From: Jelly Jia <Jelly.Jia@cixtech.com>
To: vkoul@kernel.org, robh@kernel.org, krzk+dt@kernel.org,
	conor+dt@kernel.org, robin.murphy@arm.com
Cc: devicetree@vger.kernel.org, Frank.Li@kernel.org,
	cix-kernel-upstream@cixtech.com, dmaengine@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, Jelly.Jia@cixtech.com
Subject: [PATCH v3 0/6] dmaengine: arm-dma350: Add slave support and CIX Sky1 integration
Date: Mon, 12 Oct 2026 16:41:49 +0800	[thread overview]
Message-ID: <20261012084155.2547480-1-Jelly.Jia@cixtech.com> (raw)

Hello,

This series adds slave transfer support to the Arm DMA-350 driver and
the CIX Sky1 SoC integration around it.

Patch 1 fixes the CH_CTRL_USESRCTRIGIN definition: the source trigger
enable bit is bit 25, not bit 26 (which is the destination trigger
enable bit). Unchanged since v1.

Patch 2 adds slave transfer support to the Arm DMA-350 driver:
scatter-gather and cyclic preparation, command-list allocation,
per-channel resource mapping and residue reporting. Slave transfers are
needed to serve peripheral requests, for example the audio FIFOs of the
CIX Sky1 audio subsystem.

Patch 3 syncs the slave command list before starting a transfer. The
command list is mapped with dma_map_single(), so without the sync a
non-coherent DMA-350 may read stale command words and the transfer
stalls after the first command.

Patch 4 documents the CIX Sky1 DMA-350 integration in the arm,dma-350
binding: the Sky1 controller keeps the generic compatible and adds a
"cix,sky1-dma350" device compatible, with a required clock, an optional
reset and an optional reserved memory region described on the controller
node.

Patch 5 adds the matching driver support, which manages those resources;
slave resources are mapped with dma_map_resource() and translated by the
DMA API through the parent bus dma-ranges.

Patch 6 adds the two Sky1 instances (FCH and AUDSS) to the SoC
devicetree, each under a simple-bus node describing the bus integration.

Changes since v2:
- Patches 4 and 5 no longer configure the Sky1 channel interrupt gate.
  Thanks to Conor Dooley for pointing out that the gate is upstream of
  the device and must not be routed through the driver: the driver has
  no CIX match data, no syscon register access and no system resume
  hook for it, the binding does not describe a cix,irq-router property,
  and the driver no longer selects MFD_SYSCON.
- Patch 4 now requires a clock for the CIX compatible instead of
  constraining a property of the generic compatible.
- Patch 5 releases the reserved memory region on both registration
  failure paths.
- Patch 2 fixes two residue-reporting races: the scatter-gather residue
  re-reads the channel link pointer around the CH_XSIZE read so that a
  channel stepping to the next command cannot make the residue jump,
  and cyclic transfers report the progress inside the running period
  instead of only at period boundaries. The CH_TRIGINCFG block size
  description was corrected as well.
- Patch 3 syncs the command list with its DMA API address instead of a
  second, identical address kept in the descriptor.
- Patch 6 drops the interrupt gate property together with patch 4, and
  the two bus nodes carry no unit-address in their names: they have no
  reg, which made dtc warn.

The series is based on v7.3-rc1.

Testing:
- Built for arm64 with GCC 12.3, no new warnings; sparse clean;
  checkpatch --strict clean.
- dt_binding_check and dtbs_check pass for the new binding and nodes.
- Runtime-tested on a CIX Sky1 (Radxa Orion O6) board (v3 revision):
  both the FCH and the AUDSS DMA-350 instances probe and transfer data;
  dmatest passes on 12 channels x 1000 iterations, UART DMA transfers
  (1 MiB and 5000 B) are byte-exact, and audio playback through the
  AUDSS DMA-350 runs at nominal rate without underruns or xruns.

Link: https://lore.kernel.org/r/20261009051846.1115962-1-Jelly.Jia@cixtech.com

Assisted-by: LLM checkpatch sparse dt_binding_check dtbs_check
Signed-off-by: Jelly Jia <Jelly.Jia@cixtech.com>

Jelly Jia (6):
  dmaengine: arm-dma350: Fix source trigger bit
  dmaengine: arm-dma350: Add slave and cyclic transfer support
  dmaengine: arm-dma350: Sync the slave command list before starting
  dt-bindings: dma: arm,dma-350: Document the CIX Sky1 integration
  dmaengine: arm-dma350: Support integration clocks, resets and reserved
    memory
  arm64: dts: cix: Describe the Sky1 DMA-350 bus integration

 .../devicetree/bindings/dma/arm,dma-350.yaml  |  26 +-
 arch/arm64/boot/dts/cix/sky1.dtsi             |  68 +-
 drivers/dma/arm-dma350.c                      | 710 +++++++++++++++++-
 3 files changed, 765 insertions(+), 39 deletions(-)

-- 
2.54.0


             reply	other threads:[~2026-10-12  8:42 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-12  8:41 Jelly Jia [this message]
2026-10-12  8:41 ` [PATCH v3 1/6] dmaengine: arm-dma350: Fix source trigger bit Jelly Jia
2026-10-12 15:09   ` Frank Li
2026-10-12  8:41 ` [PATCH v3 2/6] dmaengine: arm-dma350: Add slave and cyclic transfer support Jelly Jia
2026-10-12  8:41 ` [PATCH v3 3/6] dmaengine: arm-dma350: Sync the slave command list before starting Jelly Jia
2026-10-12  8:41 ` [PATCH v3 4/6] dt-bindings: dma: arm,dma-350: Document the CIX Sky1 integration Jelly Jia
2026-10-12 19:06   ` Conor Dooley
2026-10-12  8:41 ` [PATCH v3 5/6] dmaengine: arm-dma350: Support integration clocks, resets and reserved memory Jelly Jia
2026-10-12  8:41 ` [PATCH v3 6/6] arm64: dts: cix: Describe the Sky1 DMA-350 bus integration Jelly Jia
2026-10-12 19:07   ` Conor Dooley

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20261012084155.2547480-1-Jelly.Jia@cixtech.com \
    --to=jelly.jia@cixtech.com \
    --cc=Frank.Li@kernel.org \
    --cc=cix-kernel-upstream@cixtech.com \
    --cc=conor+dt@kernel.org \
    --cc=devicetree@vger.kernel.org \
    --cc=dmaengine@vger.kernel.org \
    --cc=krzk+dt@kernel.org \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=robh@kernel.org \
    --cc=robin.murphy@arm.com \
    --cc=vkoul@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox

all inboxes | Powered by JetHome®