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([179.179.244.163]) by smtp.gmail.com with ESMTPSA id a1e0cc1a2514c-99003f230b8sm6830180241.8.2026.10.12.11.41.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Oct 2026 11:41:57 -0700 (PDT) From: Vinicius Pedrosa To: linusw@kernel.org Cc: wens@kernel.org, jernej.skrabec@gmail.com, samuel@sholland.org, andre.przywara@arm.com, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 2/2] pinctrl: sunxi: a733-r: use the A733 I/O voltage fields Date: Mon, 12 Oct 2026 15:41:29 -0300 Message-ID: <20261012184130.548261-3-vinicius.eduardo.pedrosa@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261012184130.548261-1-vinicius.eduardo.pedrosa@gmail.com> References: <20261012184130.548261-1-vinicius.eduardo.pedrosa@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The A733 R-PIO shares the A523-R descriptor, and with it the A523 inverted one-bit encoding and the access to PIO_POW_MOD_CTL. Its SGPIO_POW_MOD_SEL has two-bit fields instead, and the manual documents no control register at offset 0x344. With PL in fixed 3.3 V mode, as read on a Radxa Cubie A7Z (0x000aaaaa), running the old helper on the host with a 3.3 V request for PL gives 0x000aaaab, which is fixed 1.8 V. This was not run on the board. Give the A733-R its own descriptor with the PL and PM fields, and leave the A523-R as it is. Fixes: 31d68e10381c ("pinctrl: sunxi: a523-r: add a733-r compatible string") Signed-off-by: Vinicius Pedrosa --- drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c | 26 +++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c b/drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c index cffc1e53eef1..1aa7f32035e1 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c @@ -30,11 +30,33 @@ static struct sunxi_pinctrl_desc a523_r_pinctrl_data = { .pin_base = PL_BASE, }; +/* + * The A733 R-PIO has the A523 one's layout, but its SGPIO_POW_MOD_SEL uses + * two-bit fields, and the manual documents no control register at offset 0x344. + */ +static const u32 a733_r_io_bias_masks[SUNXI_PINCTRL_MAX_BANKS] = { + [0] = GENMASK(1, 0), /* PL */ + [1] = GENMASK(3, 2), /* PM */ +}; + +static struct sunxi_pinctrl_desc a733_r_pinctrl_data = { + .irq_banks = ARRAY_SIZE(a523_r_irq_bank_map), + .irq_bank_map = a523_r_irq_bank_map, + .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL_2BIT, + .io_bias_masks = a733_r_io_bias_masks, + .pin_base = PL_BASE, +}; + static int a523_r_pinctrl_probe(struct platform_device *pdev) { + struct sunxi_pinctrl_desc *desc = &a523_r_pinctrl_data; + + if (of_device_is_compatible(pdev->dev.of_node, + "allwinner,sun60i-a733-r-pinctrl")) + desc = &a733_r_pinctrl_data; + return sunxi_pinctrl_dt_table_init(pdev, a523_r_nr_bank_pins, - a523_r_irq_bank_muxes, - &a523_r_pinctrl_data, + a523_r_irq_bank_muxes, desc, SUNXI_PINCTRL_NCAT2_REG_LAYOUT); } -- 2.43.0