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Mon, 12 Oct 2026 12:33:24 -0700 (PDT) From: Adrian Schlegel To: tony.luck@intel.com, bp@alien8.de Cc: x86@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, Adrian Schlegel Subject: [PATCH v3] x86/mce: Do not treat cache hierarchy errors as memory errors Date: Mon, 12 Oct 2026 21:33:05 +0200 Message-ID: <20261012193305.38931-1-me@adrianschlegel.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261003222012.19685-1-me@adrianschlegel.com> References: <20261003222012.19685-1-me@adrianschlegel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit On Intel and Zhaoxin, mce_is_memory_error() also returns true for cache hierarchy errors. All callers expect it to report memory errors only. The CEC uses it to count corrected DRAM errors. A corrected cache error only names the cache line that was affected, not a faulty DRAM page. With a faulty CPU core, the CEC therefore soft-offlines healthy pages. On an i9-9900K this caused about 500 soft-offline attempts per hour. Report only memory controller errors on Intel and Zhaoxin, as is already done for AMD. Fixes: fa92c5869426 ("x86, mce: Support memory error recovery for both UCNA and Deferred error in machine_check_poll") Signed-off-by: Adrian Schlegel --- v3: - Shorten and wrap commit message (Boris, Tony) - Refer to the SDM section by name instead of number (Tony) v2: - Fix mce_is_memory_error() itself instead of adding a CEC-local helper (Tony) - v1: https://lore.kernel.org/r/20260927151904.30524-1-me@adrianschlegel.com Tested with mce-inject (sw) in a VM with an Intel CPU model. A corrected cache error (status 0xcc5ffc0000100179) is no longer counted and its page stays online. A corrected memory controller error (status 0x8c0000000000009f) is still counted and its page soft-offlined. arch/x86/kernel/cpu/mce/core.c | 18 +++++------------- 1 file changed, 5 insertions(+), 13 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index ab469605f..54ed053fa 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -540,21 +540,13 @@ bool mce_is_memory_error(struct mce *m) case X86_VENDOR_INTEL: case X86_VENDOR_ZHAOXIN: /* - * Intel SDM Volume 3B - 15.9.2 Compound Error Codes + * Intel SDM Volume 3B "Compound Error Codes". * - * Bit 7 of the MCACOD field of IA32_MCi_STATUS is used for - * indicating a memory error. Bit 8 is used for indicating a - * cache hierarchy error. The combination of bit 2 and bit 3 - * is used for indicating a `generic' cache hierarchy error - * But we can't just blindly check the above bits, because if - * bit 11 is set, then it is a bus/interconnect error - and - * either way the above bits just gives more detail on what - * bus/interconnect error happened. Note that bit 12 can be - * ignored, as it's the "filter" bit. + * Memory controller errors have an MCACOD of 000F 0000 1MMM CCCC: + * bit 7 set, bits 8-11 and 13-15 clear. Bit 12 is the "filter" + * bit and is ignored. */ - return (m->status & 0xef80) == BIT(7) || - (m->status & 0xef00) == BIT(8) || - (m->status & 0xeffc) == 0xc; + return (m->status & 0xef80) == BIT(7); default: return false; -- 2.55.0