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Tue, 13 Oct 2026 03:30:28 -0700 (PDT) Received: from QCOM-eG0v1AUPpu.na.qualcomm.com ([2a01:e0a:830:450:d108:3895:812b:662a]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a18be964dfsm349955115e9.7.2026.10.13.03.30.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Oct 2026 03:30:27 -0700 (PDT) From: Loic Poulain Subject: [PATCH v2 0/6] i2c: qcom-cci: Runtime capability detection and improved read/write Date: Tue, 13 Oct 2026 12:30:24 +0200 Message-Id: <20261013-cci-imp-v2-0-6873326b44a3@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAEAIzmoC/0WNQQ6CMBREr0L+2pL202jrynsYFlCq/MRSaKHRE O5uxUQ3k7zJ5M0K0QayEc7FCsEmiuSHDHgowPTNcLeMusyAHI9co2bGECM3MtU2lZIV11oi5PU Y7I2eu+lafznYacnC+V/2FGcfXvtbEp92FwvO5U+cBOMM8dQJNK1UqC8+xnJamofxzpU5oN627 Q36A0cyugAAAA== X-Change-ID: 20260929-cci-imp-8ba384309942 To: Robert Foss , Andi Shyti , Konrad Dybcio Cc: linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Loic Poulain X-Mailer: b4 0.14.2 X-Authority-Analysis: v=2.4 cv=VqC2kO2n c=1 sm=1 tr=0 ts=6ace0846 cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=fqBssBKcfzBu9c0AyzoA:9 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 X-Proofpoint-GUID: RtUHt6mryAD7gFMq6r_XE0XiAruYjm-V X-Proofpoint-ORIG-GUID: RtUHt6mryAD7gFMq6r_XE0XiAruYjm-V X-Proofpoint-Spam-Info: AW1haW4tMjYxMDEzMDA0MSBTYWx0ZWRfX9y8PNxlEGZaE cgnQuX/TfsDSR95qs/NU6ZizWXV5df0QQVGno3H2i5nO/H7aBrrsD1PthgfKlxMr/4zakGcXWy6 i8dZuypnQgCBmaEPpRJK5Y8bdwe9frk= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDEzMDA0MSBTYWx0ZWRfX7LqcNSWgzMPH yZr/PHJ9BnB1A9lfZF2T/tG8yMoNqSOz9f1qSFmLAynH+R7IxQdNzEUvLjqsuegCVT8q4J+OtRq V9uCZ6CDmdbM1xr+EkC1Vjz+9C7Ej5Aig7A7jIFy/2dl/Sb0PUfIh/ViqvF0bFFur/NhjRxtLGk 1mzYQZvx32u0RSxG1TBP8cF+sV2hWICuv3QZHhO3NgxJOvaoZ5nZksCML1yIlIUIxrVis5qHmC7 M/hVUQpkfZwd8SPv6yqK7Eo6CuxJuS7yM86BrXR/OPw79F4/sSNhhgpGwNh3bYQAI6AUSFGV9fX x7gwVX970xAw0W+YytfeqSAxo/p55UOe/BsGxQ98d7ByQN1Me/462zxS7z0cHxnrD0y+w7jd27+ oOYeG3bM0APnZEW48P4yfNhsxCSDIm6j+D4VRWWripvqpVLhwFDPTSCbpcF+OFKNTfiWCKcSufr aMup7uUNwWrz+OjxI4A== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-13_01,2026-10-09_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 bulkscore=0 lowpriorityscore=0 spamscore=0 adultscore=0 phishscore=0 priorityscore=1501 malwarescore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610080000 definitions=main-2610130041 Improves the Qualcomm CCI I2C driver read/write in different ways: - Capabilities (queue sizes, max transfer lengths, supported I2C mode) are currently hardcoded per DT compatible string in a handful of cci_data instances. Patch 4 replaces the static per-compatible structs with a single version-sorted capability catalog resolved at runtime from CCI_HW_VERSION. - The driver only supported single-command writes, capped at 11 bytes regardless of how much space the command queue actually has. Patches 2 and 5 factor out the write-command queueing into a reusable helper and then add burst-write support, chunking longer writes across the whole queue instead of a single command's payload. - The FIFO read path hardcoded a fixed 12-byte limit unrelated to the actual per-revision FIFO size, with a special-cased drain loop. Patch 6 simplify the FIFO read/drain-loop and derive the read-side limits from each revision's FIFO size - Add burst-read support using threshold interrupts, allowing reads of arbitrary size by draining the FIFO incrementally during the transfer. Also add overflow and underflow IRQ reporting, as queue/fifo limits are now derived from the hardware capabilities and exercised more aggressively. Support for unbounded write transfers using the threshold IRQ mechanism is planned as a follow-up and not part of this series. Signed-off-by: Loic Poulain --- Changes in v2: - Split the HALT_ACK reset fix out into its own patch (Andi) - Fix a typo in the "Detect capabilities from CCI_HW_VERSION" commit message (Andi) - Use GENMASK()/FIELD_GET() to decode the CCI_HW_VERSION fields (Konrad) - Derive the number of masters from the DT i2c-bus subnodes instead of encoding it per compatible string (Konrad) - Add burst read support via RD_THRESHOLD/RD_PAUSE IRQs - Link to v1: https://lore.kernel.org/r/20261004-cci-imp-v1-0-227d12cb4829@oss.qualcomm.com --- Loic Poulain (6): i2c: qcom-cci: Factor out write command queue programming i2c: qcom-cci: Handle and report queue overflow/underflow interrupts i2c: qcom-cci: Detect capabilities from CCI_HW_VERSION at runtime i2c: qcom-cci: Add burst write support i2c: qcom-cci: Extend i2c read limits based on CCI revision i2c: qcom-cci: Add burst read support drivers/i2c/busses/i2c-qcom-cci.c | 429 +++++++++++++++++++++++++++++--------- 1 file changed, 325 insertions(+), 104 deletions(-) --- base-commit: d6dc536a4c8bb99dd822bc349a9e801be7ea81c9 change-id: 20260929-cci-imp-8ba384309942 Best regards, -- Loic Poulain