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Tue, 13 Oct 2026 03:30:32 -0700 (PDT) X-Received: by 2002:a05:620a:4689:b0:93e:5312:3c96 with SMTP id af79cd13be357-93ebd20e0c1mr2147140185a.26.1791887432174; Tue, 13 Oct 2026 03:30:32 -0700 (PDT) Received: from QCOM-eG0v1AUPpu.na.qualcomm.com ([2a01:e0a:830:450:d108:3895:812b:662a]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a18be964dfsm349955115e9.7.2026.10.13.03.30.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Oct 2026 03:30:30 -0700 (PDT) From: Loic Poulain Date: Tue, 13 Oct 2026 12:30:26 +0200 Subject: [PATCH v2 2/6] i2c: qcom-cci: Handle and report queue overflow/underflow interrupts Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261013-cci-imp-v2-2-6873326b44a3@oss.qualcomm.com> References: <20261013-cci-imp-v2-0-6873326b44a3@oss.qualcomm.com> In-Reply-To: <20261013-cci-imp-v2-0-6873326b44a3@oss.qualcomm.com> To: Robert Foss , Andi Shyti , Konrad Dybcio Cc: linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Loic Poulain X-Mailer: b4 0.14.2 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDEzMDA0MSBTYWx0ZWRfXyzzE1XhPqc5w 1kvTulyaeoKeJ72ec6R3+4nxGgmqdj01y0gENiCADE3xHg3C5GdhkC89mE9NdQueMoH7OSP2Pgo N8puuW5R9xIFowfBdf7Y1LKRA/5PfCq3lPgaHfOZZAi/O6dKPFmBYvdBu9039VIVssnsAlSdje9 QCz4gNYzi3Eha9VlnfckFBqnoX5cTXlZTKbN93b9BkzDf7ghcC9VuVT4fjARB+6s8YBgCsxxu91 nkh7tR8ckmZ6IBoQ+wgFm+xqtyK66d6BdkMA61eLBjgEhFWFm2FjnYYg2omab/9It/9EXp8eyEV 1EodXu/pVLYWcPy+9AYwkNQMAtkN42/3BIaXz9e+dplwzu0+99RH5J+kOxCnDkTr4erYA9JiXAY tylAAiwtRIDWjWKh8LeYB9xVLNZY82r/hwMxy9I2KLqOhqf8OuSp2anM2beinZZBj0FNyBDgJfm ZqvDpum56mg3WXohzjw== X-Authority-Analysis: v=2.4 cv=JN+uIMKb c=1 sm=1 tr=0 ts=6ace0849 cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=L19FZshse16xndK5FkAA:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 X-Proofpoint-Spam-Info: AW1haW4tMjYxMDEzMDA0MSBTYWx0ZWRfX8TjR/MWi9MKQ CkDyDejOMAmeee27gD7iQyqrVQkGmF2y37/MF/EgxJ49i2fq6+Y3tfXwmEJTmt+eQaURmhS+d2g Ji/aD89IuF/TWzVLuCtDc0byf3f+mA4= X-Proofpoint-ORIG-GUID: pNBmDw9uFlPNrrtUQn7i-j0vThlnCHd8 X-Proofpoint-GUID: pNBmDw9uFlPNrrtUQn7i-j0vThlnCHd8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-13_01,2026-10-09_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 priorityscore=1501 adultscore=0 suspectscore=0 phishscore=0 impostorscore=0 lowpriorityscore=0 clxscore=1015 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610080000 definitions=main-2610130041 CCI_IRQ_STATUS_0_I2C_Mx_ERROR aggregates the per-queue overflow and underflow bits together with NACK_ERR, and all of them were handled the same way: report -EIO and halt the queue. There was no way to tell a NACK apart from a FIFO overflow/underflow in the logs. Decode the individual overflow/underflow bits for each queue and report them with dev_warn_ratelimited() as such errors are not expected in normal operation. Signed-off-by: Loic Poulain --- drivers/i2c/busses/i2c-qcom-cci.c | 34 ++++++++++++++++++++++++++++++---- 1 file changed, 30 insertions(+), 4 deletions(-) diff --git a/drivers/i2c/busses/i2c-qcom-cci.c b/drivers/i2c/busses/i2c-qcom-cci.c index 3304760411082b72e10e529a2bd66361e100fa06..099da0069251681cc52e351fb656bd73e78a96c9 100644 --- a/drivers/i2c/busses/i2c-qcom-cci.c +++ b/drivers/i2c/busses/i2c-qcom-cci.c @@ -54,10 +54,18 @@ #define CCI_IRQ_STATUS_0 0xc0c #define CCI_IRQ_STATUS_0_I2C_M0_RD_DONE BIT(0) #define CCI_IRQ_STATUS_0_I2C_M0_Q0_REPORT BIT(4) +#define CCI_IRQ_STATUS_0_I2C_M0_Q0_UNDERFLOW BIT(5) +#define CCI_IRQ_STATUS_0_I2C_M0_Q0_OVERFLOW BIT(6) #define CCI_IRQ_STATUS_0_I2C_M0_Q1_REPORT BIT(8) +#define CCI_IRQ_STATUS_0_I2C_M0_Q1_UNDERFLOW BIT(9) +#define CCI_IRQ_STATUS_0_I2C_M0_Q1_OVERFLOW BIT(10) #define CCI_IRQ_STATUS_0_I2C_M1_RD_DONE BIT(12) #define CCI_IRQ_STATUS_0_I2C_M1_Q0_REPORT BIT(16) +#define CCI_IRQ_STATUS_0_I2C_M1_Q0_UNDERFLOW BIT(17) +#define CCI_IRQ_STATUS_0_I2C_M1_Q0_OVERFLOW BIT(18) #define CCI_IRQ_STATUS_0_I2C_M1_Q1_REPORT BIT(20) +#define CCI_IRQ_STATUS_0_I2C_M1_Q1_UNDERFLOW BIT(21) +#define CCI_IRQ_STATUS_0_I2C_M1_Q1_OVERFLOW BIT(22) #define CCI_IRQ_STATUS_0_RST_DONE_ACK BIT(24) #define CCI_IRQ_STATUS_0_I2C_M0_Q0Q1_HALT_ACK BIT(25) #define CCI_IRQ_STATUS_0_I2C_M1_Q0Q1_HALT_ACK BIT(26) @@ -190,22 +198,40 @@ static irqreturn_t cci_isr(int irq, void *dev) writel(reset, cci->base + CCI_RESET_CMD); if (unlikely(val & CCI_IRQ_STATUS_0_I2C_M0_ERROR)) { + cci->master[0].status = -EIO; + if (val & CCI_IRQ_STATUS_0_I2C_M0_Q0_NACK_ERR || val & CCI_IRQ_STATUS_0_I2C_M0_Q1_NACK_ERR) cci->master[0].status = -ENXIO; - else - cci->master[0].status = -EIO; + + if (val & CCI_IRQ_STATUS_0_I2C_M0_Q0_OVERFLOW) + dev_warn_ratelimited(cci->dev, "master 0 queue 0 overflow\n"); + if (val & CCI_IRQ_STATUS_0_I2C_M0_Q0_UNDERFLOW) + dev_warn_ratelimited(cci->dev, "master 0 queue 0 underflow\n"); + if (val & CCI_IRQ_STATUS_0_I2C_M0_Q1_OVERFLOW) + dev_warn_ratelimited(cci->dev, "master 0 queue 1 overflow\n"); + if (val & CCI_IRQ_STATUS_0_I2C_M0_Q1_UNDERFLOW) + dev_warn_ratelimited(cci->dev, "master 0 queue 1 underflow\n"); writel(CCI_HALT_REQ_I2C_M0_Q0Q1, cci->base + CCI_HALT_REQ); ret = IRQ_HANDLED; } if (unlikely(val & CCI_IRQ_STATUS_0_I2C_M1_ERROR)) { + cci->master[1].status = -EIO; + if (val & CCI_IRQ_STATUS_0_I2C_M1_Q0_NACK_ERR || val & CCI_IRQ_STATUS_0_I2C_M1_Q1_NACK_ERR) cci->master[1].status = -ENXIO; - else - cci->master[1].status = -EIO; + + if (val & CCI_IRQ_STATUS_0_I2C_M1_Q0_OVERFLOW) + dev_warn_ratelimited(cci->dev, "master 1 queue 0 overflow\n"); + if (val & CCI_IRQ_STATUS_0_I2C_M1_Q0_UNDERFLOW) + dev_warn_ratelimited(cci->dev, "master 1 queue 0 underflow\n"); + if (val & CCI_IRQ_STATUS_0_I2C_M1_Q1_OVERFLOW) + dev_warn_ratelimited(cci->dev, "master 1 queue 1 overflow\n"); + if (val & CCI_IRQ_STATUS_0_I2C_M1_Q1_UNDERFLOW) + dev_warn_ratelimited(cci->dev, "master 1 queue 1 underflow\n"); writel(CCI_HALT_REQ_I2C_M1_Q0Q1, cci->base + CCI_HALT_REQ); ret = IRQ_HANDLED; -- 2.34.1