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Tue, 13 Oct 2026 03:30:36 -0700 (PDT) X-Received: by 2002:a05:620a:2a14:b0:93b:d7ed:ff3d with SMTP id af79cd13be357-93ebd2aa64cmr1935913985a.63.1791887433429; Tue, 13 Oct 2026 03:30:33 -0700 (PDT) Received: from QCOM-eG0v1AUPpu.na.qualcomm.com ([2a01:e0a:830:450:d108:3895:812b:662a]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a18be964dfsm349955115e9.7.2026.10.13.03.30.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Oct 2026 03:30:32 -0700 (PDT) From: Loic Poulain Date: Tue, 13 Oct 2026 12:30:27 +0200 Subject: [PATCH v2 3/6] i2c: qcom-cci: Detect capabilities from CCI_HW_VERSION at runtime Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261013-cci-imp-v2-3-6873326b44a3@oss.qualcomm.com> References: <20261013-cci-imp-v2-0-6873326b44a3@oss.qualcomm.com> In-Reply-To: <20261013-cci-imp-v2-0-6873326b44a3@oss.qualcomm.com> To: Robert Foss , Andi Shyti , Konrad Dybcio Cc: linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Loic Poulain X-Mailer: b4 0.14.2 X-Authority-Analysis: v=2.4 cv=VqC2kO2n c=1 sm=1 tr=0 ts=6ace084d cx=c_pps a=oc9J++0uMp73DTRD5QyR2A==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=8R-5LDRAFMUVkZqLBecA:9 a=QEXdDO2ut3YA:10 a=iYH6xdkBrDN1Jqds4HTS:22 X-Proofpoint-GUID: v3P9jKkyF3OQmeLIQJTCVdfgqb0EKAIB X-Proofpoint-ORIG-GUID: v3P9jKkyF3OQmeLIQJTCVdfgqb0EKAIB X-Proofpoint-Spam-Info: AW1haW4tMjYxMDEzMDA0MSBTYWx0ZWRfX8Fil6YviZuBF 8/2Rz57ibAFUGiWstffjI0Cr+H2dI06rM+m2ZE810PbSAENYyIo29cs5Y/O1V7clp7y0JWRxP1T efrGAn4UQjIr+tzqZMNPa4hWYMCniCM= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDEzMDA0MSBTYWx0ZWRfXzO1l7V0+yZDc m6h2saiK6mi76g9eyhMivTAwThMVVE7+PFXwYPBpyJ7vYlsjVWxHIUF1Y58WTACRCiV4BTqtoeS RP5THpzy8sXmdApOPKaV7E8XP8vSwEYVFu3UPuU7amiwobzlC0iVoiJQIGLg0cCgDLAtC9lkbvn 1sIQ6HiV7ekiDL/wlGBm7WoVwCJHVzm9Ad1f03DxV6CGGOX8rwNk0LRH0j3NxNX2/HbmJPhAaiA N/yANNy2W47VwlIJgnu2IREpsLR98CTRxSEXM/+tzQaAaCMBCaAJYUR1YPpQj5rguaFMKVM0dwI DikOjPeRn5ZcO31dNhb7+8OigbjFD4gisK6TB5yED3hJLqdmf+Q7MbFSecqHdhVuoyZOlzN/HPm 8J9gaQVUqiqDfvtCkYo5Dk8gER9kddBS+UVhN4SvBf58oC+xfLUm69WyA2mcjdp8Ird7etWFJTO DYiTy6O+DylJnpGiAEw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-13_01,2026-10-09_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 bulkscore=0 lowpriorityscore=0 spamscore=0 adultscore=0 phishscore=0 priorityscore=1501 malwarescore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610080000 definitions=main-2610130041 In theory, every SoC integrating a CCI revision that differs from an existing one should introduce a dedicated compatible string. In practice, most CCI instances still fall back to the msm8996 compat (v1.4.0), one of the oldest supported versions. In order to take advantage of capabilities introduced in later versions, such as larger queues (v1.6.0) or threshold IRQ support (v1.7.0), we need to properly distinguish the different variants. Replace the static per-compatible cci_data definitions with a version-sorted capability table keyed by (hw_major, hw_minor). During probe, read CCI hardware revision register and select the newest capability entry whose version is less than or equal to the detected hardware revision. This allows revisions to automatically inherit the closest supported capability set without requiring additional compatible strings. Several compatibles that currently fall back to the msm8996 configuration (e.g. sdm845, sm8250 and sm8450) will now resolve to the corresponding capability tier, gaining access to their larger queue sizes instead of the conservative msm8996 defaults. - v1.2.x CCI increase I2C write payload + burst write support - v1.6.x CCI has increased queue sizes (64,16) -> (128,32) - v1.7.x CCI introduces threshold IRQs (leveraged later) - v1.10.x CCI increase queue 0 size (128) -> (1024) Suggested-by: Konrad Dybcio Signed-off-by: Loic Poulain --- drivers/i2c/busses/i2c-qcom-cci.c | 162 +++++++++++++++++++++++++------------- 1 file changed, 106 insertions(+), 56 deletions(-) diff --git a/drivers/i2c/busses/i2c-qcom-cci.c b/drivers/i2c/busses/i2c-qcom-cci.c index 099da0069251681cc52e351fb656bd73e78a96c9..3bca29f1d2699375a0348b18a5a2e646a59fd94c 100644 --- a/drivers/i2c/busses/i2c-qcom-cci.c +++ b/drivers/i2c/busses/i2c-qcom-cci.c @@ -2,6 +2,7 @@ // Copyright (c) 2012-2016, The Linux Foundation. All rights reserved. // Copyright (c) 2017-2022 Linaro Limited. +#include #include #include #include @@ -14,6 +15,10 @@ #include #define CCI_HW_VERSION 0x0 +#define CCI_HW_VERSION_MAJOR_MASK GENMASK(31, 28) +#define CCI_HW_VERSION_MINOR_MASK GENMASK(27, 16) +#define CCI_HW_VERSION_STEP_MASK GENMASK(15, 0) +#define QCOM_CCI_VERSION(major, minor) .hw_major = (major), .hw_minor = (minor) #define CCI_RESET_CMD 0x004 #define CCI_RESET_CMD_MASK 0x0f73f3f7 #define CCI_RESET_CMD_M0_MASK 0x000003f1 @@ -133,7 +138,8 @@ struct cci_master { }; struct cci_data { - unsigned int num_masters; + u16 hw_major; + u16 hw_minor; struct i2c_adapter_quirks quirks; u16 queue_size[NUM_QUEUES]; /* Highest I2C mode supported by this variant. */ @@ -144,6 +150,7 @@ struct cci { struct device *dev; void __iomem *base; unsigned int irq; + unsigned int num_masters; const struct cci_data *data; struct clk_bulk_data *clocks; int nclocks; @@ -245,7 +252,7 @@ static int cci_halt(struct cci *cci, u8 master_num) struct cci_master *master; u32 val; - if (master_num >= cci->data->num_masters) { + if (master_num >= cci->num_masters) { dev_err(cci->dev, "Unsupported master idx (%u)\n", master_num); return -EINVAL; } @@ -371,7 +378,7 @@ static int cci_init(struct cci *cci) writel(val, cci->base + CCI_IRQ_MASK_0); - for (i = 0; i < cci->data->num_masters; i++) { + for (i = 0; i < cci->num_masters; i++) { int mode = cci->master[i].mode; const struct hw_params *hw; @@ -615,7 +622,7 @@ static int cci_get_required_rate(struct cci *cci, unsigned long *rate) for (int ri = 0; ri < NUM_CCI_CLK_RATES; ri++) { bool supported = true; - for (int i = 0; i < cci->data->num_masters; i++) { + for (int i = 0; i < cci->num_masters; i++) { int mode = cci->master[i].mode; if (!cci->master[i].cci) @@ -690,6 +697,81 @@ static const struct dev_pm_ops qcom_cci_pm = { SET_RUNTIME_PM_OPS(cci_suspend_runtime, cci_resume_runtime, NULL) }; +/* Hardware capabilities, ascending by version major,minor */ +static const struct cci_data cci_hw_catalog[] = { + { + QCOM_CCI_VERSION(1, 0), + .max_mode = I2C_MODE_FAST, + .queue_size = { 64, 16 }, + .quirks = { + .max_write_len = 10, + .max_read_len = 12, + }, + }, + { + QCOM_CCI_VERSION(1, 2), + .max_mode = I2C_MODE_FAST_PLUS, + .queue_size = { 64, 16 }, + .quirks = { + .max_write_len = 11, + .max_read_len = 12, + }, + }, + { + QCOM_CCI_VERSION(1, 6), + .max_mode = I2C_MODE_FAST_PLUS, + .queue_size = { 128, 32 }, + .quirks = { + .max_write_len = 11, + .max_read_len = 12, + }, + }, + { + QCOM_CCI_VERSION(1, 7), + .max_mode = I2C_MODE_FAST_PLUS, + .queue_size = { 128, 32 }, + .quirks = { + .max_write_len = 11, + .max_read_len = 12, + }, + }, + { + QCOM_CCI_VERSION(1, 10), + .max_mode = I2C_MODE_FAST_PLUS, + .queue_size = { 1024, 32 }, + .quirks = { + .max_write_len = 11, + .max_read_len = 12, + }, + }, +}; + +static void cci_detect_hw_caps(struct cci *cci, u32 hw_version) +{ + u8 major = FIELD_GET(CCI_HW_VERSION_MAJOR_MASK, hw_version); + u16 minor = FIELD_GET(CCI_HW_VERSION_MINOR_MASK, hw_version); + u16 step = FIELD_GET(CCI_HW_VERSION_STEP_MASK, hw_version); + const struct cci_data *data = &cci_hw_catalog[0]; + int i; + + for (i = 0; i < ARRAY_SIZE(cci_hw_catalog); i++) { + if (cci_hw_catalog[i].hw_major > major || + (cci_hw_catalog[i].hw_major == major && cci_hw_catalog[i].hw_minor > minor)) + break; + data = &cci_hw_catalog[i]; + } + + dev_dbg(cci->dev, "CCI HW version %u.%u.%u, using caps tier %u.%u\n", + major, minor, step, data->hw_major, data->hw_minor); + + cci->data = data; + + for (i = 0; i < cci->num_masters; i++) { + if (cci->master[i].cci) + cci->master[i].adap.quirks = &cci->data->quirks; + } +} + static int cci_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -705,9 +787,6 @@ static int cci_probe(struct platform_device *pdev) cci->dev = dev; platform_set_drvdata(pdev, cci); - cci->data = device_get_match_data(dev); - if (!cci->data) - return -ENOENT; for_each_available_child_of_node(dev->of_node, child) { struct cci_master *master; @@ -719,14 +798,16 @@ static int cci_probe(struct platform_device *pdev) continue; } - if (idx >= cci->data->num_masters) { + if (idx >= NUM_MASTERS) { dev_err(dev, "%pOF invalid 'reg' value: %u (max is %u)", - child, idx, cci->data->num_masters - 1); + child, idx, NUM_MASTERS - 1); continue; } + if (idx >= cci->num_masters) + cci->num_masters = idx + 1; + master = &cci->master[idx]; - master->adap.quirks = &cci->data->quirks; master->adap.algo = &cci_algo; master->adap.dev.parent = dev; master->adap.dev.of_node = of_node_get(child); @@ -777,10 +858,6 @@ static int cci_probe(struct platform_device *pdev) if (ret && ret != -ENODEV) return dev_err_probe(dev, ret, "failed to add OPP table\n"); - ret = cci_set_core_rate(cci); - if (ret) - return ret; - ret = cci_enable_clocks(cci); if (ret < 0) return ret; @@ -799,7 +876,11 @@ static int cci_probe(struct platform_device *pdev) } val = readl(cci->base + CCI_HW_VERSION); - dev_dbg(dev, "CCI HW version = 0x%08x", val); + cci_detect_hw_caps(cci, val); + + ret = cci_set_core_rate(cci); + if (ret) + goto disable_clocks; ret = cci_reset(cci); if (ret < 0) @@ -810,7 +891,7 @@ static int cci_probe(struct platform_device *pdev) pm_runtime_set_active(dev); pm_runtime_enable(dev); - for (i = 0; i < cci->data->num_masters; i++) { + for (i = 0; i < cci->num_masters; i++) { if (!cci->master[i].cci) continue; @@ -844,7 +925,7 @@ static void cci_remove(struct platform_device *pdev) struct cci *cci = platform_get_drvdata(pdev); int i; - for (i = 0; i < cci->data->num_masters; i++) { + for (i = 0; i < cci->num_masters; i++) { if (cci->master[i].cci) { i2c_del_adapter(&cci->master[i].adap); of_node_put(cci->master[i].adap.dev.of_node); @@ -856,51 +937,20 @@ static void cci_remove(struct platform_device *pdev) pm_runtime_set_suspended(&pdev->dev); } -static const struct cci_data cci_v1_data = { - .num_masters = 1, - .queue_size = { 64, 16 }, - .quirks = { - .max_write_len = 10, - .max_read_len = 12, - }, - .max_mode = I2C_MODE_FAST, -}; - -static const struct cci_data cci_v1_5_data = { - .num_masters = 2, - .queue_size = { 64, 16 }, - .quirks = { - .max_write_len = 10, - .max_read_len = 12, - }, - .max_mode = I2C_MODE_FAST, -}; - -static const struct cci_data cci_v2_data = { - .num_masters = 2, - .queue_size = { 64, 16 }, - .quirks = { - .max_write_len = 11, - .max_read_len = 12, - }, - .max_mode = I2C_MODE_FAST_PLUS, -}; - static const struct of_device_id cci_dt_match[] = { - { .compatible = "qcom,msm8226-cci", .data = &cci_v1_data}, - { .compatible = "qcom,msm8953-cci", .data = &cci_v2_data}, - { .compatible = "qcom,msm8974-cci", .data = &cci_v1_5_data}, - { .compatible = "qcom,msm8996-cci", .data = &cci_v2_data}, - + { .compatible = "qcom,msm8226-cci" }, + { .compatible = "qcom,msm8953-cci" }, + { .compatible = "qcom,msm8974-cci" }, + { .compatible = "qcom,msm8996-cci" }, /* * Legacy compatibles kept for backwards compatibility. * Do not add any new ones unless they introduce a new config */ - { .compatible = "qcom,msm8916-cci", .data = &cci_v1_data}, - { .compatible = "qcom,sdm845-cci", .data = &cci_v2_data}, - { .compatible = "qcom,sm8250-cci", .data = &cci_v2_data}, - { .compatible = "qcom,sm8450-cci", .data = &cci_v2_data}, + { .compatible = "qcom,msm8916-cci" }, + { .compatible = "qcom,sdm845-cci" }, + { .compatible = "qcom,sm8250-cci" }, + { .compatible = "qcom,sm8450-cci" }, {} }; MODULE_DEVICE_TABLE(of, cci_dt_match); -- 2.34.1