From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 629374B8262; Tue, 13 Oct 2026 16:37:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791909475; cv=none; b=mFjMe7P/yWV6SCsMG62fVA2p1I/s2aI2b+MHRPEqXk4qUwwWBFg212mszr1hQtH4cf1i9fva+5n+CkMkPo0wN9QpW42Fe+npAFEM0M1r6YqSMdxCrY82M7Pi0fv+WiB7ftMTbtpCcBcxg82fgaSj29QJdVtPi6kzD8GurE/I49g= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791909475; c=relaxed/simple; bh=FLqniTou4JQnWTRSbyJYhIPig7BctcqFyncv79mGFio=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=sEpvtrdaqhnhoIUdQUwCE9epNaqehbJKRt2fh0Z4TzuXVk2vSHhpSxOdclzR7eWg0/lpyOAn2SQsY2yu+ejWTaFdJHHZnbh+dxD9OdN4oR8YjKGOZwDSZHlJFrTTL9WHdNkLFXzWNhCY//Iq3V4UQbs2pukIwgKo+a563OK5FRc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=YIKOXM8D; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="YIKOXM8D" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1791909480; x=1823445480; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=FLqniTou4JQnWTRSbyJYhIPig7BctcqFyncv79mGFio=; b=YIKOXM8DxDwjsZDeNpxJ5+fiPy1DE9uR7cz9JJ9nK7XLHyf7MyTNP81Y UqGN9C67v3TOJVX6z7XJeDct7qa/av17PKJb3FNxaVesVcmgGKY3u66cB +Nqb50zC3Kfi/YVOGzU1RddCWkl+51bsImpEnycR4rzfwFGuYHoC/ly6U Ex/Sl7ui2K761e7AImFMnFJX6TX2ZzYSXZpP1vfFNbNOECyq0hl1zUvft slOo+/Kt6JoMOUZ3Gc707i0dRqSPXm//HhIksMiKeFQ3EFU0Z3CkbhAFb Q8pMpPqvi6R0sdjR6RIqaa1Uve2qK5OF+2z2jRxGNgVgoRDXtKcixeVPY w==; X-CSE-ConnectionGUID: YRaOoJawRqi8KbUm6KZLmw== X-CSE-MsgGUID: wfiL0GUHT5K9ipfyTLsTFQ== X-IronPort-AV: E=Sophos;i="6.27,156,1787036400"; d="scan'208";a="75325077" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2026 09:37:54 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.87.152) by chn-vm-ex3.mchp-main.com (10.10.87.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.49; Tue, 13 Oct 2026 09:37:47 -0700 Received: from ROU-LL-M19942.mpu32.int (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 13 Oct 2026 09:37:43 -0700 From: Cyrille Pitchen Date: Tue, 13 Oct 2026 18:37:23 +0200 Subject: [PATCH v11 1/5] dt-bindings: gpu: add bindings for the Microchip GFX2D GPU Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-ID: <20261013-cpitchen-mainline_gfx2d-v11-1-7527f2efab0a@microchip.com> References: <20261013-cpitchen-mainline_gfx2d-v11-0-7527f2efab0a@microchip.com> In-Reply-To: <20261013-cpitchen-mainline_gfx2d-v11-0-7527f2efab0a@microchip.com> To: David Airlie , Simona Vetter , "Maarten Lankhorst" , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nicolas Ferre , "Alexandre Belloni" , Claudiu Beznea , Russell King CC: , , , , Cyrille Pitchen , Conor Dooley X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1772; i=cyrille.pitchen@microchip.com; h=from:subject:message-id; bh=FLqniTou4JQnWTRSbyJYhIPig7BctcqFyncv79mGFio=; b=owGbwMvMwCXmf6yzKqEsVIbxtFoSQ9a5uIA3SpfCeE5Jfjxf9OD+BKmvLCbH9i+4LyZnva90I aubz7n1HaUsDGJcDLJiiiyH3mztzTz+6rHdK1EpmDmsTCBDGLg4BWAi3tMZ/ue7Op681lYi9LJt R5L90RqGnQV21Ut+BG0/v3fL+e9XldwY/nsI7rF3rIpN3Prz58ry3XY/qz/xdMRfVNuvaPtnwaz 7yawA X-Developer-Key: i=cyrille.pitchen@microchip.com; a=openpgp; fpr=7A21115D7D6026585D0E183E0EF12AA1BFAC073D The Microchip GFX2D GPU is embedded in the SAM9X60 and SAM9X7 SoC family. Describe how the GFX2D GPU is integrated in these SoCs, including register space, interrupt and clock. Acked-by: Conor Dooley Reviewed-by: Nicolas Ferre Signed-off-by: Cyrille Pitchen --- .../bindings/gpu/microchip,sam9x60-gfx2d.yaml | 46 ++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/microchip,sam9x60-gfx2d.yaml b/Documentation/devicetree/bindings/gpu/microchip,sam9x60-gfx2d.yaml new file mode 100644 index 000000000000..1c0faef83900 --- /dev/null +++ b/Documentation/devicetree/bindings/gpu/microchip,sam9x60-gfx2d.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpu/microchip,sam9x60-gfx2d.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip GFX2D GPU + +maintainers: + - Cyrille Pitchen + +properties: + compatible: + enum: + - microchip,sam9x60-gfx2d + - microchip,sam9x7-gfx2d + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + #include + #include + gpu@f0018000 { + compatible = "microchip,sam9x60-gfx2d"; + reg = <0xf0018000 0x100>; + interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 36>; + }; + +... -- 2.53.0