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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3537cab27d5sm46081248eec.17.2026.10.13.00.10.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Oct 2026 00:10:12 -0700 (PDT) From: Varadarajan Narayanan Date: Tue, 13 Oct 2026 12:39:45 +0530 Subject: [PATCH v2 3/3] arm64: dts: qcom: ipq5210: Enable interconnect capability to clock controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261013-icc-v2-3-196b219e25c1@oss.qualcomm.com> References: <20261013-icc-v2-0-196b219e25c1@oss.qualcomm.com> In-Reply-To: <20261013-icc-v2-0-196b219e25c1@oss.qualcomm.com> To: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Konrad Dybcio Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Varadarajan Narayanan , Konrad Dybcio X-Mailer: b4 0.14.3 X-Proofpoint-GUID: nOVcdAv55vd-3D80R5yLK4Hf4jdOPSyE X-Authority-Analysis: v=2.4 cv=JJuuIMKb c=1 sm=1 tr=0 ts=6acdd956 cx=c_pps a=cFYjgdjTJScbgFmBucgdfQ==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=JR9XVsisKQFD673mhBYA:9 a=QEXdDO2ut3YA:10 a=scEy_gLbYbu1JhEsrz4S:22 X-Proofpoint-Spam-Info: AW1haW4tMjYxMDEzMDAyOCBTYWx0ZWRfXy4vkFYP1FYJ4 +ORNddFMEsGjCNVisSwL7qE6wozUNz2/CJsmchwoQcZ3L509DJaC4xpFQwTgtWVX4sF7q7iLpPQ QC52gQBrQPr5x9KI8N3eU9J19rWczdU= X-Proofpoint-ORIG-GUID: nOVcdAv55vd-3D80R5yLK4Hf4jdOPSyE X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDEzMDAyOCBTYWx0ZWRfXxrClwqs0xDbi 8JnL4FrHMgNnF96/Jpy5Tq+jU4M2lmrGTVYOnGYQC5LRV703L2aJc5pFF4tdMlKOKmLc9BF9DuS 3lFyBqblt3m3bgUC02+FkkdDrwc3Spr0aPMBRzPUMf+ySt1aep8I41TiZWaK1LjDLiKaBLVfVSQ OfmkOHnoeJ6YDQ7LXf77j28yuvF4LxTiC5TOIRw5QaTLswED08N/rkpce4DEKVld2V7ifzSi+Mv fMYHNSWZvQe1AcJugnWPqNj4WF7h0LRHIWvIKaFjP0lHXIcf6N+27bqvMv3MJkmt5dBi/HA+SMx tVc3DGarNPXarXinyFCt+pohc5IHt6G+aK35xbibKg4NCLzL+mtC+469i1obqqx4eZKSc8R/KA9 tIizyRkj1TilgVvpFp8YiNNAKtMI2b4p+wSN6BCpIwbtVgy7Rz7iqgCGEiZAE+InHSoQzsZTun/ jkk6B37No3l44comiKA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-13_01,2026-10-09_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 clxscore=1015 malwarescore=0 lowpriorityscore=0 impostorscore=0 adultscore=0 phishscore=0 priorityscore=1501 spamscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610080000 definitions=main-2610130028 Add 'interconnect-cells' to the clock controller node. This will be used for enabling NOC related clocks using icc-clk framework. Reviewed-by: Konrad Dybcio Signed-off-by: Varadarajan Narayanan --- arch/arm64/boot/dts/qcom/ipq5210.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5210.dtsi b/arch/arm64/boot/dts/qcom/ipq5210.dtsi index 2cdc10529c48..20e8b240642c 100644 --- a/arch/arm64/boot/dts/qcom/ipq5210.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5210.dtsi @@ -152,6 +152,7 @@ gcc: clock-controller@1800000 { <0>; #clock-cells = <1>; #reset-cells = <1>; + #interconnect-cells = <1>; }; tcsr_mutex: hwlock@1905000 { -- 2.34.1