Re: [PATCH 3/4] dt-bindings: clock: ipq9650-apss-clk: Add IPQ9650 apss clock controller

[Krzysztof Kozlowski <krzk@kernel.org>]

On Wed, Oct 07, 2026 at 12:20:46PM +0530, Kathiravan Thirumoorthy wrote:
> The APSS clock controller on IPQ9650 provides the CPU and L3 clocks and
> has a register space separate from the GCC. The four Cortex-A55 cores,
> the Cortex-A78 core and the L3 are each clocked by their own Zonda PLL,
> selected through a glitch-free mux whose parents are XO, GPLL0 and the
> corresponding PLL. The L3 needs to be scaled along with the CPUs, so the
> controller is also an interconnect provider.
> 
> Add the binding, the clock indices for the Cortex-A78 (gold) cluster to
> the shared APSS header, and the interconnect IDs for the CPU and L3
> nodes.
> 
> Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
> ---
>  .../bindings/clock/qcom,ipq9650-apss-clk.yaml      | 58 ++++++++++++++++++++++
>  include/dt-bindings/clock/qcom,apss-ipq.h          |  5 ++
>  include/dt-bindings/interconnect/qcom,ipq9650.h    |  4 ++
>  3 files changed, 67 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9650-apss-clk.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9650-apss-clk.yaml
> new file mode 100644
> index 000000000000..6b47183edd56
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9650-apss-clk.yaml
> @@ -0,0 +1,58 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/qcom,ipq9650-apss-clk.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm APSS IPQ9650 Clock Controller
> +
> +maintainers:
> +  - Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
> +
> +description:
> +  The APSS clock controller provides the CPU and L3 clocks on IPQ9650 and
> +  has a register space separate from the GCC. The four Cortex-A55 cores,
> +  the Cortex-A78 core and the L3 are each clocked by their own Zonda PLL.
> +  Each clock is selected through a glitch-free mux (GFM) whose parents are
> +  XO, GPLL0 and the corresponding PLL.
> +
> +properties:
> +  compatible:
> +    enum:
> +      - qcom,ipq9650-apss-clk
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    items:
> +      - description: Reference to the XO clock.
> +      - description: Reference to the GPLL0 clock.

Why do you need a new file? Looks exactly the same as existing
ipq5424-apss-clk.


Best regards,
Krzysztof