From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6200E423EAA for ; Mon, 12 Oct 2026 22:38:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791844708; cv=none; b=sCycK4mx8B1nhDY7nFLi+yCvKuU4Mws9Sis9GU1JUh96U7fWFe4ehnclqdq53k5F91WGHW4XuH+5avOkji051Z7BswcwS18Ugeceo2aDFnMHm7hoZ+I1FFx68berSgNe89bVWt3zJulnULQpg+uROcu9pag5bpGXFT5JLOyWtb4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791844708; c=relaxed/simple; bh=iemir4/bJvID1L2kuPWuIgRZmoTsm805wNnKuGPgf04=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=OQhOur9+MmGxADt2mhPzLLRsb/jSLtxtCdq5mxFarYdHLfwJq4GpzzsQOrdTGCGmlpLcj+kgOI8r7e0CViST2bc40EwkxBYAq1sWP8QU4MLtUleJQVMHWVUsbjBZU0vcqkmRWxQFqLQH0YtPfkYB00Db6vKva/2yL7ue3bX6r3g= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=qFKSwFRL; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="qFKSwFRL" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1791844700; bh=iemir4/bJvID1L2kuPWuIgRZmoTsm805wNnKuGPgf04=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=qFKSwFRLGxtqO6u5h1LLzhfGvCfuOX+IklBzSfb4e1YBntOuu5lVI2689MbnxGIVd e3CPfcpr/X6K8DPWHA3jxZdZH6iL/YNyWtyiU4JCI1n/MQ5SKTIwGj6H39lhIXrzgC +DZC39B8AfXt7VRgBAIS0uEttoevM5wv90+DufxVqqW5WHubAowyER0u3XvUOtGdVQ qbybt8zXWvj11y82kRYyZTwGsAXCA1d0kaiOuAHttxLBJCCGSF8MAVE5BnXWAS82bz EBCQgxFbKDD/quTniK4h0/YSJzgVYnQo+exmAkndBR3qU2apr2pnlfTAs6NfRtET1/ 4IZEOj/NBuqGQ== Received: from localhost (unknown [100.64.0.241]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange secp256r1 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with ESMTPSA id 0C2F017E092C; Tue, 13 Oct 2026 00:38:20 +0200 (CEST) From: Cristian Ciocaltea Date: Tue, 13 Oct 2026 01:37:42 +0300 Subject: [PATCH v2 2/8] drm/vc4: hdmi: Bump BCM2835 max pixel clock to 165 MHz Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261013-vc4-common-scramb-v2-2-a41d15e131ad@collabora.com> References: <20261013-vc4-common-scramb-v2-0-a41d15e131ad@collabora.com> In-Reply-To: <20261013-vc4-common-scramb-v2-0-a41d15e131ad@collabora.com> To: Maxime Ripard , Dave Stevenson , =?utf-8?q?Ma=C3=ADra_Canal?= , Raspberry Pi Kernel Maintenance , Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 Historically, the HSM clock for BCM2835 was fixed at 163.7 MHz. Since the pixel clock had to be at least 1% below the HSM clock, it was capped at 162 MHz. Since commit cd4cb49dc5bb ("drm/vc4: hdmi: Adjust HSM clock rate depending on pixel rate"), the HSM clock rate is set to pixel clock * 101 / 100. For a 165 MHz pixel clock, this gives an HSM rate of 166.65 MHz, which, per Dave Stevenson, the hardware can handle without issues. Increase the max pixel clock to 165 MHz, which matches the maximum TMDS character rate of HDMI 1.0 through 1.2. Suggested-by: Dave Stevenson Signed-off-by: Cristian Ciocaltea --- drivers/gpu/drm/vc4/vc4_hdmi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c index 8e4623ccc4f8..e61f1b694dbe 100644 --- a/drivers/gpu/drm/vc4/vc4_hdmi.c +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c @@ -1507,7 +1507,7 @@ static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder, * users are able to use pixel clocks closer to HSM's, namely for * 1920x1200@60Hz. So it was decided to have leave a 1% margin between * both clocks. Which, for RPi0-3 implies a maximum pixel clock of - * 162MHz. + * 165MHz. * * Additionally, the AXI clock needs to be at least 25% of * pixel clock, but HSM ends up being the limiting factor. @@ -3363,7 +3363,7 @@ static const struct vc4_hdmi_variant bcm2835_variant = { .encoder_type = VC4_ENCODER_TYPE_HDMI0, .debugfs_name = "hdmi_regs", .card_name = "vc4-hdmi", - .max_pixel_clock = 162000000, + .max_pixel_clock = HDMI_1_0_TMDS_CHAR_RATE_MAX_HZ, .registers = vc4_hdmi_fields, .num_registers = ARRAY_SIZE(vc4_hdmi_fields), -- 2.55.0