From: Pengfei Zhang <zhangfeionline@gmail.com>
To: Maxime Chevallier <maxime.chevallier@bootlin.com>,
Andrew Lunn <andrew+netdev@lunn.ch>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@kernel.org>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Jose Abreu <joabreu@synopsys.com>,
EricChan <chenchuangyu@xiaomi.com>,
Simon Horman <horms@kernel.org>,
zhangpengfei16@xiaomi.com, netdev@vger.kernel.org,
linux-stm32@st-md-mailman.stormreply.com,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: [PATCH net] net: stmmac: xgmac: do not treat TBU as a TX event
Date: Tue, 13 Oct 2026 10:47:47 +0800 [thread overview]
Message-ID: <20261013024747.2688984-1-zhangfeionline@gmail.com> (raw)
Commit 8d07a7930434 ("net: stmmac: xgmac: Do not enable TBU interrupt")
removed TBUE from the default DMA interrupt mask, but did not remove the
TBU check from dwxgmac2_dma_interrupt().
TBU is set whenever a TX channel runs out of descriptors. Since TBUE is
not enabled and only enabled bits are cleared, the TBU status bit is
never cleared. As a result, TBU stays set on every idle TX channel,
regardless of whether there is any TX traffic.
With a shared interrupt, stmmac_dma_interrupt() checks all channels,
so every interrupt from any source schedules TX NAPI on every idle TX
channel.
Only use TI to trigger TX processing.
Fixes: 8d07a7930434 ("net: stmmac: xgmac: Do not enable TBU interrupt")
Signed-off-by: Pengfei Zhang <zhangfeionline@gmail.com>
---
Tested on a board with 8 RX/TX DMA channels behind one shared
interrupt. A peer sends 10k UDP packets/s to the board and the board
sends nothing back, so there should be almost no TX work. Every idle
channel reads DMA_CH_STATUS 0x4 (TBU only).
Per second, averaged over 10 s:
before after
hw interrupts 9071 8580
tx_normal_irq_n 72572 1
tx_clean ~73000 9
- hw interrupts: the shared interrupt line, from /proc/interrupts.
Unchanged, the RX watchdog sets the rate.
- tx_normal_irq_n (ethtool -S): how often dwxgmac2_dma_interrupt()
returned handle_tx. Before the fix every interrupt reports it for
all 8 channels.
- tx_clean (ethtool -S): stmmac_tx_clean() runs, i.e. TX NAPI polls.
Each spurious handle_tx schedules one. What is left after the fix
is real TX and the TX coalesce timer. The "before" value is from a
separate run with the same setup.
No packet loss before or after.
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
index ff83858ebc..0a6e82a155 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
@@ -346,7 +346,7 @@ static int dwxgmac2_dma_interrupt(struct stmmac_priv *priv,
u64_stats_update_end(&stats->syncp);
ret |= handle_rx;
}
- if (likely(intr_status & (XGMAC_TI | XGMAC_TBU))) {
+ if (likely(intr_status & XGMAC_TI)) {
u64_stats_update_begin(&stats->syncp);
u64_stats_inc(&stats->tx_normal_irq_n[chan]);
u64_stats_update_end(&stats->syncp);
--
2.54.0
next reply other threads:[~2026-10-13 2:48 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-13 2:47 Pengfei Zhang [this message]
2026-10-13 2:49 ` netdev-bot+sinfo
2026-10-13 6:09 ` Pengfei Zhang
2026-10-13 4:55 ` Pengfei Zhang
2026-10-13 6:40 ` Maxime Chevallier
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