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([39.170.101.209]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3ab36fdc75esm19541303a91.12.2026.10.12.20.32.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Oct 2026 20:32:13 -0700 (PDT) From: Zxyan Zhu To: andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@kernel.org, kuba@kernel.org, pabeni@redhat.com, maxime.chevallier@bootlin.com Cc: mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, richardcochran@gmail.com, muhammad.nazim.amirul.nazle.asmade@altera.com, rohan.g.thomas@altera.com, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next v8 0/3] net: stmmac: dwxgmac2: timestamp interrupt support + Agilex5 fix Date: Tue, 13 Oct 2026 11:32:04 +0800 Message-Id: <20261013033207.1684328-1-zxyan0222@gmail.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit This series adds auxiliary snapshot (EXTTS) interrupt support to DWXGMAC2/DWXLGMAC2, fixes a stale TSIS race on the Agilex5 cross-timestamp path that the new handler would otherwise expose, and guards the shared aux snapshot handler against a zero channel mask. Patch 1 makes smtg_crosststamp() complete on the persistent ATSNS count instead of the transient TSIS bit, waits for the FIFO clear to complete, and holds aux_ts_lock across the whole trigger/poll/drain sequence so a concurrent EXTTS request cannot flush the snapshot FIFO mid-flight. Patch 2 guards the shared aux snapshot handler against a zero channel mask: ilog2() is applied to the mask without a zero check, and ilog2(0) yields an out-of-range event index that ptp_clock_event() feeds to test_bit() unchecked from hard IRQ context. Patch 3 adds a dedicated DWXGMAC2 timestamp interrupt handler. The XGMAC hwif entries used the generic ops, whose callback read the wrong register and whose enable mask omitted the timestamp interrupt, so the clock advertised the aux snapshot channels but no event was ever delivered. XGMAC_TSIE is not enabled by default; it is armed on demand from the EXTTS enable/disable path through a new callback, and the handler only touches the FIFO while the interrupt is armed and while no cross-timestamp owns it. The interrupt is disarmed on suspend and unregister and re-armed on resume. v1: https://lore.kernel.org/netdev/20260806-dwxgmac2-timestamp-irq-v1-1-c051c79c9d90@gmail.com/ v2: https://lore.kernel.org/netdev/20260810100221.9166-1-zxyan0222@gmail.com/ v3: https://lore.kernel.org/netdev/20260818132722.1852876-1-zxyan0222@gmail.com/ v4: https://lore.kernel.org/netdev/20260902131441.322167-1-zxyan0222@gmail.com/ v5: https://lore.kernel.org/netdev/20260910081020.86227-1-zxyan0222@gmail.com/ v6: https://lore.kernel.org/netdev/20260929073553.4136336-1-zxyan0222@gmail.com/ v7: https://lore.kernel.org/netdev/20261004120526.2728564-1-zxyan0222@gmail.com/ v8: - Gate the handler's FIFO drain on XGMAC_TSIE being armed; the handler runs for every MAC interrupt and must not touch the FIFO while the timestamp interrupt is disarmed. - Hold aux_ts_lock across the whole EXTTS enable, including the FIFO clear poll, so the re-arm cannot interleave with a suspend. - Drain an in-flight handler with stmmac_sync_timestamp_irq() when the FIFO is handed to the cross-timestamp and on the EXTTS disable path. - Roll a failed EXTTS enable back in hardware and software on the FIFO-clear timeout, and drop the EXTTS state when the resume re-arm cannot restore the channel. - Disarm XGMAC_TSIE on suspend and unregister; re-arm it on resume. - Initialise aux_ts_lock in probe and destroy it in remove, so it is valid for the whole device lifetime. - Only clear the software state in the resume-failure teardown, since the auxiliary snapshot register differs on DWMAC_CORE_MAC100/GMAC. -- 2.43.0