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Tue, 13 Oct 2026 10:27:19 +0000 From: Changhuang Liang To: Brian Masney , Jerome Brunet , Stephen Boyd , Philipp Zabel , Emil Renner Berthing Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Hal Feng , Changhuang Liang Subject: [PATCH v1 0/6] Add System-0 CRG for JHB100 SoC Date: Tue, 13 Oct 2026 03:27:01 -0700 Message-Id: <20261013102707.9207-1-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: NT0PR01CA0027.CHNPR01.prod.partner.outlook.cn (2406:e500:c510:c::20) To ZQ4PR01MB1202.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:17::6) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ4PR01MB1202:EE_|ZQ4PR01MB1234:EE_ X-MS-Office365-Filtering-Correlation-Id: 50f0d121-cff3-489c-c3de-08df29148f6e X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|52116014|1800799024|376014|366016|23010399003|38350700014|56012099006|261009221727099003|261009223027099003|261009223327099003|261009220027099003|261009221227099003|10067099003|18002099003; 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The original series had too many patches, and there was a lot of similar logic among the patches. To reduce the burden of repeating similar comments and reviews, the original series of patches was split up and a new series was established. This series is based on the clk-next branch. Changes since previous submission: - Change RESET_STARFIVE_JHB100 from select to imply. - Fix the external clock index to JH71X0_EXT_CLK_FLAG, and add JH71X0_EXT_CLK(_n) to define the external clock index. - Remove CLK_IS_CRITICAL usage in sys0. - Add a static_assert to check at compile time whether the internal clock and the external clock overlap in sys0. - Remove 'power_domain" from 'struct jh71x0_crg_domain_info'. - Register the reset device using devm_auxiliary_device_create(). - Obtain 'struct jh71x0_reset_adev *' via dev_get_platdata(). - Streamline the reset patch, keeping only the sys0 part. Changhuang Liang (6): clk: starfive: jh7110-sys: Fix memory leak in reset controller register clk: starfive: jh71x0: Move reset controller registration to jh71x0 common code clk: starfive: jh71x0: Add generic CRG probe helper clk: starfive: Add JHB100 System-0 clock generator driver reset: starfive: jh71x0: Support discontiguous reset IDs reset: starfive: Add StarFive JHB100 System-0 reset driver MAINTAINERS | 13 ++ drivers/clk/starfive/Kconfig | 12 +- drivers/clk/starfive/Makefile | 2 + .../clk/starfive/clk-starfive-jh7110-aon.c | 2 +- .../clk/starfive/clk-starfive-jh7110-isp.c | 2 +- .../clk/starfive/clk-starfive-jh7110-stg.c | 2 +- .../clk/starfive/clk-starfive-jh7110-sys.c | 57 +------ .../clk/starfive/clk-starfive-jh7110-vout.c | 2 +- drivers/clk/starfive/clk-starfive-jh7110.h | 4 - drivers/clk/starfive/clk-starfive-jh71x0.c | 120 +++++++++++++- drivers/clk/starfive/clk-starfive-jh71x0.h | 23 +++ .../clk/starfive/clk-starfive-jhb100-sys0.c | 148 ++++++++++++++++++ drivers/reset/starfive/Kconfig | 9 ++ drivers/reset/starfive/Makefile | 1 + .../reset/starfive/reset-starfive-jh7110.c | 19 ++- .../reset/starfive/reset-starfive-jh71x0.c | 99 ++++++++++-- .../reset/starfive/reset-starfive-jh71x0.h | 19 +++ .../reset/starfive/reset-starfive-jhb100.c | 75 +++++++++ include/soc/starfive/reset-starfive-jh71x0.h | 10 +- 19 files changed, 524 insertions(+), 95 deletions(-) create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-sys0.c create mode 100644 drivers/reset/starfive/reset-starfive-jhb100.c -- 2.25.1