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Wysocki" , Bjorn Andersson , Andy Shevchenko , Randy Dunlap , dmaengine@vger.kernel.org (open list:DMA GENERIC OFFLOAD ENGINE SUBSYSTEM), linux-kernel@vger.kernel.org (open list) Cc: imx@lists.linux.dev, Frank Li Subject: [PATCH 1/1] dmaengine: shdma: move shdma_chan and shdma_desc structs to private header Date: Tue, 13 Oct 2026 16:34:23 -0400 Message-ID: <20261013203433.337893-1-Frank.Li@oss.nxp.com> X-Mailer: git-send-email 2.43.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: CY8P220CA0013.NAMP220.PROD.OUTLOOK.COM (2603:10b6:930:46::9) To GV2PR04MB11799.eurprd04.prod.outlook.com (2603:10a6:150:2cf::9) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: GV2PR04MB11799:EE_|ZR6PR04MB375776:EE_ X-MS-Office365-Filtering-Correlation-Id: 22a79334-fd8f-4b18-1296-08df29696e64 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|366016|1800799024|19092799006|23010399003|56012099006|261009223027099003|11063799006|18002099003|10067099003|6133799003; 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These structs are only used internally by the shdma driver and do not need to be exposed to external users. Prepare to make struct dma_async_tx_descriptor private. Signed-off-by: Frank Li --- drivers/dma/sh/shdma-base.c | 2 +- drivers/dma/sh/shdma.h | 80 +++++++++++++++++++++++++++++++++++++ include/linux/shdma-base.h | 80 +------------------------------------ 3 files changed, 83 insertions(+), 79 deletions(-) diff --git a/drivers/dma/sh/shdma-base.c b/drivers/dma/sh/shdma-base.c index 89a78e685b1d1..ef704a6aed233 100644 --- a/drivers/dma/sh/shdma-base.c +++ b/drivers/dma/sh/shdma-base.c @@ -20,7 +20,7 @@ #include #include -#include "../dmaengine.h" +#include "shdma.h" /* DMA descriptor control */ enum shdma_desc_status { diff --git a/drivers/dma/sh/shdma.h b/drivers/dma/sh/shdma.h index f97d80343aea4..d66d45062e9bd 100644 --- a/drivers/dma/sh/shdma.h +++ b/drivers/dma/sh/shdma.h @@ -15,11 +15,32 @@ #include #include +#include "../dmaengine.h" + #define SH_DMAE_MAX_CHANNELS 20 #define SH_DMAE_TCR_MAX 0x00FFFFFF /* 16MB */ struct device; +struct shdma_chan { + spinlock_t chan_lock; /* Channel operation lock */ + struct list_head ld_queue; /* Link descriptors queue */ + struct list_head ld_free; /* Free link descriptors */ + struct dma_chan dma_chan; /* DMA channel */ + struct device *dev; /* Channel device */ + void *desc; /* buffer for descriptor array */ + int desc_num; /* desc count */ + size_t max_xfer_len; /* max transfer length */ + int id; /* Raw id of this channel */ + int irq; /* Channel IRQ */ + int slave_id; /* Client ID for slave DMA */ + int real_slave_id; /* argument passed to filter function */ + int hw_req; /* DMA request line for slave DMA - + * same as MID/RID, used with DT + */ + enum shdma_pm_state pm_state; +}; + struct sh_dmae_chan { struct shdma_chan shdma_chan; const struct sh_dmae_slave_config *config; /* Slave DMA configuration */ @@ -30,6 +51,13 @@ struct sh_dmae_chan { dma_addr_t slave_addr; }; +struct shdma_dev { + struct dma_device dma_dev; + struct shdma_chan **schan; + const struct shdma_ops *ops; + size_t desc_size; +}; + struct sh_dmae_device { struct shdma_dev shdma_dev; struct sh_dmae_chan *chan[SH_DMAE_MAX_CHANNELS]; @@ -41,6 +69,58 @@ struct sh_dmae_device { u32 chcr_ie_bit; }; +struct shdma_desc { + struct list_head node; + struct dma_async_tx_descriptor async_tx; + enum dma_transfer_direction direction; + size_t partial; + dma_cookie_t cookie; + int chunks; + int mark; + bool cyclic; /* used as cyclic transfer */ +}; + +/** + * struct shdma_ops - simple DMA driver operations + * @desc_completed: return true, if this is the descriptor, that just has + * completed (atomic) + * @halt_channel: stop DMA channel operation (atomic) + * @channel_busy: return true, if the channel is busy (atomic) + * @slave_addr: return slave DMA address + * @desc_setup: set up the hardware specific descriptor portion (atomic) + * @set_slave: bind channel to a slave + * @setup_xfer: configure channel hardware for operation (atomic) + * @start_xfer: start the DMA transfer (atomic) + * @embedded_desc: return Nth struct shdma_desc pointer from the + * descriptor array + * @chan_irq: process channel IRQ, return true if a transfer has + * completed (atomic) + */ +struct shdma_ops { + bool (*desc_completed)(struct shdma_chan *, struct shdma_desc *); + void (*halt_channel)(struct shdma_chan *); + bool (*channel_busy)(struct shdma_chan *); + dma_addr_t (*slave_addr)(struct shdma_chan *); + int (*desc_setup)(struct shdma_chan *, struct shdma_desc *, + dma_addr_t, dma_addr_t, size_t *); + int (*set_slave)(struct shdma_chan *, int, dma_addr_t, bool); + int (*setup_xfer)(struct shdma_chan *, int); + void (*start_xfer)(struct shdma_chan *, struct shdma_desc *); + struct shdma_desc *(*embedded_desc)(void *, int); + bool (*chan_irq)(struct shdma_chan *, int); + size_t (*get_partial)(struct shdma_chan *, struct shdma_desc *); +}; + +#define shdma_for_each_chan(c, d, i) for (i = 0, c = (d)->schan[0]; \ + i < (d)->dma_dev.chancnt; c = (d)->schan[++i]) + +int shdma_request_irq(struct shdma_chan *, int, unsigned long, const char *); +bool shdma_reset(struct shdma_dev *sdev); +void shdma_chan_probe(struct shdma_dev *sdev, struct shdma_chan *schan, int id); +void shdma_chan_remove(struct shdma_chan *schan); +int shdma_init(struct device *dev, struct shdma_dev *sdev, int chan_num); +void shdma_cleanup(struct shdma_dev *sdev); + struct sh_dmae_regs { u32 sar; /* SAR / source address */ u32 dar; /* DAR / destination address */ diff --git a/include/linux/shdma-base.h b/include/linux/shdma-base.h index b6827c06d332f..a7e6184728f8d 100644 --- a/include/linux/shdma-base.h +++ b/include/linux/shdma-base.h @@ -43,85 +43,9 @@ struct shdma_slave { int slave_id; }; -struct shdma_desc { - struct list_head node; - struct dma_async_tx_descriptor async_tx; - enum dma_transfer_direction direction; - size_t partial; - dma_cookie_t cookie; - int chunks; - int mark; - bool cyclic; /* used as cyclic transfer */ -}; - -struct shdma_chan { - spinlock_t chan_lock; /* Channel operation lock */ - struct list_head ld_queue; /* Link descriptors queue */ - struct list_head ld_free; /* Free link descriptors */ - struct dma_chan dma_chan; /* DMA channel */ - struct device *dev; /* Channel device */ - void *desc; /* buffer for descriptor array */ - int desc_num; /* desc count */ - size_t max_xfer_len; /* max transfer length */ - int id; /* Raw id of this channel */ - int irq; /* Channel IRQ */ - int slave_id; /* Client ID for slave DMA */ - int real_slave_id; /* argument passed to filter function */ - int hw_req; /* DMA request line for slave DMA - same - * as MID/RID, used with DT */ - enum shdma_pm_state pm_state; -}; - -/** - * struct shdma_ops - simple DMA driver operations - * @desc_completed: return true, if this is the descriptor, that just has - * completed (atomic) - * @halt_channel: stop DMA channel operation (atomic) - * @channel_busy: return true, if the channel is busy (atomic) - * @slave_addr: return slave DMA address - * @desc_setup: set up the hardware specific descriptor portion (atomic) - * @set_slave: bind channel to a slave - * @setup_xfer: configure channel hardware for operation (atomic) - * @start_xfer: start the DMA transfer (atomic) - * @embedded_desc: return Nth struct shdma_desc pointer from the - * descriptor array - * @chan_irq: process channel IRQ, return true if a transfer has - * completed (atomic) - */ -struct shdma_ops { - bool (*desc_completed)(struct shdma_chan *, struct shdma_desc *); - void (*halt_channel)(struct shdma_chan *); - bool (*channel_busy)(struct shdma_chan *); - dma_addr_t (*slave_addr)(struct shdma_chan *); - int (*desc_setup)(struct shdma_chan *, struct shdma_desc *, - dma_addr_t, dma_addr_t, size_t *); - int (*set_slave)(struct shdma_chan *, int, dma_addr_t, bool); - int (*setup_xfer)(struct shdma_chan *, int); - void (*start_xfer)(struct shdma_chan *, struct shdma_desc *); - struct shdma_desc *(*embedded_desc)(void *, int); - bool (*chan_irq)(struct shdma_chan *, int); - size_t (*get_partial)(struct shdma_chan *, struct shdma_desc *); -}; - -struct shdma_dev { - struct dma_device dma_dev; - struct shdma_chan **schan; - const struct shdma_ops *ops; - size_t desc_size; -}; - -#define shdma_for_each_chan(c, d, i) for (i = 0, c = (d)->schan[0]; \ - i < (d)->dma_dev.chancnt; c = (d)->schan[++i]) +struct shdma_chan; +struct shdma_dev; -int shdma_request_irq(struct shdma_chan *, int, - unsigned long, const char *); -bool shdma_reset(struct shdma_dev *sdev); -void shdma_chan_probe(struct shdma_dev *sdev, - struct shdma_chan *schan, int id); -void shdma_chan_remove(struct shdma_chan *schan); -int shdma_init(struct device *dev, struct shdma_dev *sdev, - int chan_num); -void shdma_cleanup(struct shdma_dev *sdev); #if IS_ENABLED(CONFIG_SH_DMAE_BASE) bool shdma_chan_filter(struct dma_chan *chan, void *arg); #else -- 2.43.0