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Tue, 13 Oct 2026 19:10:33 -0700 (PDT) From: Matt Turner To: Magnus Lindholm Cc: richard.henderson@linaro.org, linux-kernel@vger.kernel.org, linux-alpha@vger.kernel.org Subject: Re: [PATCH v7 4/5] alpha: decode and acknowledge Tsunami system machine checks Date: Tue, 13 Oct 2026 22:10:19 -0400 Message-ID: <20261014021020.3842132-2-mattst88@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261013211551.991723-5-linmag7@gmail.com> References: <20261013211551.991723-1-linmag7@gmail.com> <20261013211551.991723-5-linmag7@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit On Tue, Oct 13, 2026 at 23:15 +0200, Magnus Lindholm wrote: > + /* > + * Table 10-42 selects the ECC fields whenever CRE or UECC is set. > + * Mixed ECC/PCI bits do not establish which error occurred first. > + */ 10.2.5.6 says the register freezes on the first error and only LOST can be set afterwards. So mixed bits were detected together, and ordering does not come into it. > + /* HRM 10.2.5.7: PERRMASK gates latching, not just notification. */ > + > + /* Preserve each chip's transaction and the NXM source before clearing. */ The first comment is not attached to any code, and the changelog already makes the point. I would drop it. Table 10-43 gives the PERRMASK reset value as 0, all errors disabled, and Linux never writes it, so all of the PERROR handling here depends on what SRM programs. What does PERRMASK read on your ES40? > + draina(); > + tsunami_clear_errors(&live); 10.2.5.6 warns that PERROR read before the error reaches DRIR can come back with INV set. On a 670 or 630 that races with a new Pchip error we would acknowledge it with INV set and lose the transaction, along with the 660 that would have reported it. I would leave the Pchips alone outside 660/620. Reviewed-by: Matt Turner