From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from www537.your-server.de (www537.your-server.de [188.40.3.216]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B0A623A8739; Wed, 14 Oct 2026 07:17:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=188.40.3.216 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791962227; cv=none; b=loAT8ZW9tKEEQeqm6AENWpryVbBCzkFs7JIfvEA1goi8yLmpcZUGaJ50ZdB4sYjEuBUTBVtojnsWqbA39NaOSTstsBL2Wb3tVTjYe6FOEXfcPsF9jAvwkNam18l89HG+6ifBkwIH2BIanMr83UYkbrioc4uLfflYeDM85dn1CFs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791962227; c=relaxed/simple; bh=lkUvX+wDvxlrxfymv7bHffZIk4oeT5+pK9oEBppTUJQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=aY4PeSYn+H+v9F4okDJHk5DwowMZxN5qKT7Ap/iZMDdL5J0Xpzo0JZPA8uRsxrPeN+KBFK9Jy1OI14tJD87mdYGmCleS89H9/hPW5HmbHTztSxr2lnoXQZA3P0mmV/VW4FaX8+U5MBHSkJEmHohpEtEni9YH78odoGPuf+Hoj5U= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ew.tq-group.com; spf=pass smtp.mailfrom=ew.tq-group.com; dkim=pass (2048-bit key) header.d=ew.tq-group.com header.i=@ew.tq-group.com header.b=C4xdcSXt; arc=none smtp.client-ip=188.40.3.216 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ew.tq-group.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ew.tq-group.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ew.tq-group.com header.i=@ew.tq-group.com header.b="C4xdcSXt" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=ew.tq-group.com; s=default2602; h=Content-Transfer-Encoding:MIME-Version: References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To: Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID; bh=GwHJPQZUtuKCeOkSnuXK1XdvDVMXGuvW2jBkJxpDDDI=; b=C4xdcSXtqPMfrwHqnb46ICQtJK 5kVblumdICzGINHeR0jCZ3ls380221mtQCL1Z9rUAl87Po2hTiN3nSAv1MWDl4Lg91ommu9sSl4Bl mhiSYfY5TylInEb9BlyleN36OTSYoPztBUNuj4UX+G6cX8VFjv3hMawYMAfMUSbUD15rdInfZOJvo pF8T0cmn+WN9pWw+kwDGyZ4qFjDABFUI8XgkKh/Za6t6TAj0Yn/w54lShO2iVc+aLEMbb3KZZWXMm cAsHLQNUFhUddVrBCqv5K69LjOOSw52B0gPxiRKDBcF2JGjMK4CX68mGVUyFrchWqHiWqHKDLwQoj cJHnNnxg==; Received: from sslproxy02.your-server.de ([78.47.166.47]) by www537.your-server.de with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (Exim 4.96.2) (envelope-from ) id 1xGtEU-000GBv-3A; Wed, 14 Oct 2026 09:17:03 +0200 Received: from localhost ([127.0.0.1]) by sslproxy02.your-server.de with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1xGtEU-000AF0-17; Wed, 14 Oct 2026 09:17:02 +0200 From: Alexander Stein To: Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dong Aisheng Cc: Liu Ying , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux@ew.tq-group.com, Alexander Stein Subject: [PATCH v2 3/5] arm64: dts: imx8qxp: Add MIPI-LVDS combo subsystems Date: Wed, 14 Oct 2026 09:16:47 +0200 Message-ID: <20261014071657.118378-4-alexander.stein@ew.tq-group.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261014071657.118378-1-alexander.stein@ew.tq-group.com> References: <20261014071657.118378-1-alexander.stein@ew.tq-group.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Virus-Scanned: Clear (ClamAV 1.4.3/28152/Tue Oct 13 08:26:14 2026) From: Liu Ying The MIPI-LVDS combo subsystems are peripherals of pixel link MSI bus in i.MX8qxp display controller subsystem. Add the MIPI-LVDS combo subsystems. Signed-off-by: Liu Ying Signed-off-by: Alexander Stein --- Changes in v2: * None .../boot/dts/freescale/imx8qxp-ss-dc.dtsi | 4 + .../dts/freescale/imx8qxp-ss-mipi-lvds.dtsi | 443 ++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 3 + 3 files changed, 450 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8qxp-ss-mipi-lvds.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-dc.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-dc.dtsi index 647ee3348f494..9916a06669c87 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-dc.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-dc.dtsi @@ -156,10 +156,12 @@ port@1 { dc0_pixel_link0_mipi_lvds_0_pxl2dpi: endpoint@0 { reg = <0>; + remote-endpoint = <&mipi_lvds_0_pxl2dpi_dc0_pixel_link0>; }; dc0_pixel_link0_mipi_lvds_1_pxl2dpi: endpoint@1 { reg = <1>; + remote-endpoint = <&mipi_lvds_1_pxl2dpi_dc0_pixel_link0>; }; }; @@ -211,10 +213,12 @@ port@1 { dc0_pixel_link1_mipi_lvds_1_pxl2dpi: endpoint@0 { reg = <0>; + remote-endpoint = <&mipi_lvds_1_pxl2dpi_dc0_pixel_link1>; }; dc0_pixel_link1_mipi_lvds_0_pxl2dpi: endpoint@1 { reg = <1>; + remote-endpoint = <&mipi_lvds_0_pxl2dpi_dc0_pixel_link1>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-mipi-lvds.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-mipi-lvds.dtsi new file mode 100644 index 0000000000000..67f5392cfc803 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-mipi-lvds.dtsi @@ -0,0 +1,443 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 NXP + */ + +#include +#include + +/ { + mipi_lvds_0_ipg_clk: clock-mipi-lvds0-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <120000000>; + clock-output-names = "mipi_lvds_0_ipg_clk"; + }; + + mipi_lvds_1_ipg_clk: clock-mipi-lvds1-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <120000000>; + clock-output-names = "mipi_lvds_1_ipg_clk"; + }; +}; + +&dc0_pl_msi_bus { + mipi_lvds_0_irqsteer: interrupt-controller@56220000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x56220000 0x1000>; + interrupts = ; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + clocks = <&mipi_lvds_0_lis_lpcg IMX_LPCG_CLK_4>; + clock-names = "ipg"; + fsl,channel = <0>; + fsl,num-irqs = <32>; + }; + + mipi_lvds_0_csr: bus@56221000 { + compatible = "simple-pm-bus", "syscon"; + reg = <0x56221000 0x1000>; + clocks = <&mipi_lvds_0_di_mipi_lvds_regs_lpcg IMX_LPCG_CLK_4>; + clock-names = "ipg"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mipi_lvds_0_pxl2dpi: pxl2dpi { + compatible = "fsl,imx8qxp-pxl2dpi"; + fsl,sc-resource = ; + power-domains = <&pd IMX_SC_R_MIPI_0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + mipi_lvds_0_pxl2dpi_dc0_pixel_link0: endpoint@0 { + reg = <0>; + remote-endpoint = <&dc0_pixel_link0_mipi_lvds_0_pxl2dpi>; + status = "disabled"; + }; + + mipi_lvds_0_pxl2dpi_dc0_pixel_link1: endpoint@1 { + reg = <1>; + remote-endpoint = <&dc0_pixel_link1_mipi_lvds_0_pxl2dpi>; + status = "disabled"; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi>; + status = "disabled"; + }; + + mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1: endpoint@1 { + reg = <1>; + remote-endpoint = <&mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi>; + status = "disabled"; + }; + }; + }; + }; + + mipi_lvds_0_ldb: ldb { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qxp-ldb"; + clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>, + <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>; + clock-names = "pixel", "bypass"; + assigned-clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>; + assigned-clock-parents = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>; + power-domains = <&pd IMX_SC_R_LVDS_0>; + status = "disabled"; + + channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + phys = <&mipi_lvds_0_phy>; + phy-names = "lvds_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi: endpoint { + remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0>; + }; + }; + }; + + channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + phys = <&mipi_lvds_0_phy>; + phy-names = "lvds_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi: endpoint { + remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1>; + }; + }; + }; + }; + }; + + mipi_lvds_0_lis_lpcg: clock-controller@56223000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56223000 0x4>; + #clock-cells = <1>; + clocks = <&mipi_lvds_0_ipg_clk>; + clock-indices = ; + clock-output-names = "mipi_lvds_0_lis_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_0>; + }; + + mipi_lvds_0_di_mipi_lvds_regs_lpcg: clock-controller@56223004 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56223004 0x4>; + #clock-cells = <1>; + clocks = <&mipi_lvds_0_ipg_clk>; + clock-indices = ; + clock-output-names = "mipi_lvds_0_di_mipi_lvds_regs_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_0>; + }; + + mipi_lvds_0_pwm_lpcg: clock-controller@5622300c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5622300c 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_MIPI_0_PWM_0 IMX_SC_PM_CLK_PER>, + <&mipi_lvds_0_ipg_clk>, + <&mipi_lvds_0_ipg_clk>; + clock-indices = , + , + ; + clock-output-names = "mipi_lvds_0_pwm_lpcg_clk", + "mipi_lvds_0_pwm_lpcg_ipg_clk", + "mipi_lvds_0_pwm_lpcg_32k_clk"; + power-domains = <&pd IMX_SC_R_MIPI_0_PWM_0>; + }; + + mipi_lvds_0_i2c0_lpcg: clock-controller@56223010 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56223010 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_MIPI_0_I2C_0 IMX_SC_PM_CLK_PER>, + <&mipi_lvds_0_ipg_clk>; + clock-indices = , + ; + clock-output-names = "mipi_lvds_0_i2c0_lpcg_clk", + "mipi_lvds_0_i2c0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>; + }; + + mipi_lvds_0_pwm: pwm@56224000 { + compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm"; + reg = <0x56224000 0x1000>; + interrupt-parent = <&mipi_lvds_0_irqsteer>; + interrupts = <12>; + clocks = <&mipi_lvds_0_pwm_lpcg IMX_LPCG_CLK_4>, + <&mipi_lvds_0_pwm_lpcg IMX_LPCG_CLK_0>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX_SC_R_MIPI_0_PWM_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + #pwm-cells = <3>; + power-domains = <&pd IMX_SC_R_MIPI_0_PWM_0>; + status = "disabled"; + }; + + mipi_lvds_0_i2c0: i2c@56226000 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x56226000 0x1000>; + interrupt-parent = <&mipi_lvds_0_irqsteer>; + interrupts = <8>; + clocks = <&mipi_lvds_0_i2c0_lpcg IMX_LPCG_CLK_0>, + <&mipi_lvds_0_i2c0_lpcg IMX_LPCG_CLK_4>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_MIPI_0_I2C_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>; + status = "disabled"; + }; + + mipi_lvds_0_phy: phy@56228300 { + compatible = "fsl,imx8qxp-mipi-dphy"; + reg = <0x56228300 0x100>; + clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_PHY>; + clock-names = "phy_ref"; + assigned-clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_PHY>; + assigned-clock-parents = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>; + #phy-cells = <0>; + fsl,syscon = <&mipi_lvds_0_csr>; + power-domains = <&pd IMX_SC_R_MIPI_0>; + status = "disabled"; + }; + + mipi_lvds_1_irqsteer: interrupt-controller@56240000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x56240000 0x1000>; + interrupts = ; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + clocks = <&mipi_lvds_1_lis_lpcg IMX_LPCG_CLK_4>; + clock-names = "ipg"; + fsl,channel = <0>; + fsl,num-irqs = <32>; + }; + + mipi_lvds_1_csr: bus@56241000 { + compatible = "simple-pm-bus", "syscon"; + reg = <0x56241000 0x1000>; + clocks = <&mipi_lvds_1_di_mipi_lvds_regs_lpcg IMX_LPCG_CLK_4>; + clock-names = "ipg"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mipi_lvds_1_pxl2dpi: pxl2dpi { + compatible = "fsl,imx8qxp-pxl2dpi"; + fsl,sc-resource = ; + power-domains = <&pd IMX_SC_R_MIPI_1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + mipi_lvds_1_pxl2dpi_dc0_pixel_link1: endpoint@0 { + reg = <0>; + remote-endpoint = <&dc0_pixel_link1_mipi_lvds_1_pxl2dpi>; + status = "disabled"; + }; + + mipi_lvds_1_pxl2dpi_dc0_pixel_link0: endpoint@1 { + reg = <1>; + remote-endpoint = <&dc0_pixel_link0_mipi_lvds_1_pxl2dpi>; + status = "disabled"; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + mipi_lvds_1_pxl2dpi_mipi_lvds_1_ldb_ch0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_1_ldb_ch0_mipi_lvds_1_pxl2dpi>; + status = "disabled"; + }; + + mipi_lvds_1_pxl2dpi_mipi_lvds_1_ldb_ch1: endpoint@1 { + reg = <1>; + remote-endpoint = <&mipi_lvds_1_ldb_ch1_mipi_lvds_1_pxl2dpi>; + status = "disabled"; + }; + }; + }; + }; + + mipi_lvds_1_ldb: ldb { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qxp-ldb"; + clocks = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_MISC2>, + <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_BYPASS>; + clock-names = "pixel", "bypass"; + assigned-clocks = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_MISC2>; + assigned-clock-parents = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_BYPASS>; + power-domains = <&pd IMX_SC_R_LVDS_1>; + status = "disabled"; + + channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + phys = <&mipi_lvds_1_phy>; + phy-names = "lvds_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + mipi_lvds_1_ldb_ch0_mipi_lvds_1_pxl2dpi: endpoint { + remote-endpoint = <&mipi_lvds_1_pxl2dpi_mipi_lvds_1_ldb_ch0>; + }; + }; + }; + + channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + phys = <&mipi_lvds_1_phy>; + phy-names = "lvds_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + mipi_lvds_1_ldb_ch1_mipi_lvds_1_pxl2dpi: endpoint { + remote-endpoint = <&mipi_lvds_1_pxl2dpi_mipi_lvds_1_ldb_ch1>; + }; + }; + }; + }; + }; + + mipi_lvds_1_lis_lpcg: clock-controller@56243000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56243000 0x4>; + #clock-cells = <1>; + clocks = <&mipi_lvds_1_ipg_clk>; + clock-indices = ; + clock-output-names = "mipi_lvds_1_lis_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_1>; + }; + + mipi_lvds_1_di_mipi_lvds_regs_lpcg: clock-controller@56243004 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56243004 0x4>; + #clock-cells = <1>; + clocks = <&mipi_lvds_1_ipg_clk>; + clock-indices = ; + clock-output-names = "mipi_lvds_1_di_mipi_lvds_regs_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_1>; + }; + + mipi_lvds_1_pwm_lpcg: clock-controller@5624300c { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5624300c 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_MIPI_1_PWM_0 IMX_SC_PM_CLK_PER>, + <&mipi_lvds_1_ipg_clk>, + <&mipi_lvds_1_ipg_clk>; + clock-indices = , + , + ; + clock-output-names = "mipi_lvds_1_pwm_lpcg_clk", + "mipi_lvds_1_pwm_lpcg_ipg_clk", + "mipi_lvds_1_pwm_lpcg_32k_clk"; + power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>; + }; + + mipi_lvds_1_i2c0_lpcg: clock-controller@56243010 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56243010 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_PER>, + <&mipi_lvds_1_ipg_clk>; + clock-indices = , + ; + clock-output-names = "mipi_lvds_1_i2c0_lpcg_clk", + "mipi_lvds_1_i2c0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>; + }; + + mipi_lvds_1_pwm: pwm@56244000 { + compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm"; + reg = <0x56244000 0x1000>; + interrupt-parent = <&mipi_lvds_1_irqsteer>; + interrupts = <12>; + clocks = <&mipi_lvds_1_pwm_lpcg IMX_LPCG_CLK_4>, + <&mipi_lvds_1_pwm_lpcg IMX_LPCG_CLK_0>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX_SC_R_MIPI_1_PWM_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + #pwm-cells = <3>; + power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>; + status = "disabled"; + }; + + mipi_lvds_1_i2c0: i2c@56246000 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x56246000 0x1000>; + interrupt-parent = <&mipi_lvds_1_irqsteer>; + interrupts = <8>; + clocks = <&mipi_lvds_1_i2c0_lpcg IMX_LPCG_CLK_0>, + <&mipi_lvds_1_i2c0_lpcg IMX_LPCG_CLK_4>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>; + status = "disabled"; + }; + + mipi_lvds_1_phy: phy@56248300 { + compatible = "fsl,imx8qxp-mipi-dphy"; + reg = <0x56248300 0x100>; + clocks = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_PHY>; + clock-names = "phy_ref"; + assigned-clocks = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_PHY>; + assigned-clock-parents = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_BYPASS>; + #phy-cells = <0>; + fsl,syscon = <&mipi_lvds_1_csr>; + power-domains = <&pd IMX_SC_R_MIPI_1>; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index eedca1c300d64..268dd63646806 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -34,6 +34,8 @@ aliases { i2c1 = &i2c1; i2c2 = &i2c2; i2c3 = &i2c3; + mipi-dphy0 = &mipi_lvds_0_phy; + mipi-dphy1 = &mipi_lvds_1_phy; mmc0 = &usdhc1; mmc1 = &usdhc2; mmc2 = &usdhc3; @@ -351,6 +353,7 @@ map0 { #include "imx8qxp-ss-vpu.dtsi" #include "imx8qxp-ss-security.dtsi" #include "imx8qxp-ss-dc.dtsi" +#include "imx8qxp-ss-mipi-lvds.dtsi" #include "imx8qxp-ss-adma.dtsi" #include "imx8qxp-ss-conn.dtsi" #include "imx8qxp-ss-lsio.dtsi" -- 2.55.0