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Wed, 14 Oct 2026 00:23:02 -0700 (PDT) Received: from navid-pc ([2a01:4b00:a856:6220::a11]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48de3f7f8b8sm8500933f8f.35.2026.10.14.00.23.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Oct 2026 00:23:01 -0700 (PDT) From: Navid Ghahremani To: linux-arm-kernel@lists.infradead.org Cc: arnd@arndb.de, stefandoesinger@gmail.com, krzk@kernel.org, Navid Ghahremani , Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 10/24] dt-bindings: phy: Add ZTE ZX279128S PCIe PHY binding Date: Wed, 14 Oct 2026 08:20:50 +0100 Message-ID: <20261014072109.1759502-11-ghahramani.navid@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261014072109.1759502-1-ghahramani.navid@gmail.com> References: <20261014072109.1759502-1-ghahramani.navid@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add Device Tree binding for the PCIe SerDes PHY found inside the topcrm block of the ZTE ZX279128S SoC. Signed-off-by: Navid Ghahremani --- .../bindings/phy/zte,zx279128s-pcie-phy.yaml | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/zte,zx279128s-pcie-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/zte,zx279128s-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/zte,zx279128s-pcie-phy.yaml new file mode 100644 index 0000000000..7bfa363294 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/zte,zx279128s-pcie-phy.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/zte,zx279128s-pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ZTE ZX279128S PCIe PHY + +maintainers: + - Navid Ghahremani + +description: + PCIe PHY block inside the ZTE ZX279128S Top CRM. + +properties: + compatible: + const: zte,zx279128s-pcie-phy + + reg: + description: Port index (0 or 1) + items: + - enum: [0, 1] + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - "#phy-cells" + +additionalProperties: false + +examples: + - | + phy@0 { + compatible = "zte,zx279128s-pcie-phy"; + reg = <0>; + #phy-cells = <0>; + }; -- 2.55.0