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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 17/24] dt-bindings: net: Add ZTE ZX279128S Ethernet switch Date: Wed, 14 Oct 2026 08:20:57 +0100 Message-ID: <20261014072109.1759502-18-ghahramani.navid@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261014072109.1759502-1-ghahramani.navid@gmail.com> References: <20261014072109.1759502-1-ghahramani.navid@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Describe the switch, receive interrupt and per-port PHY modes and MAC addresses. Signed-off-by: Navid Ghahremani --- .../bindings/net/zte,zx279128s-gmac.yaml | 125 ++++++++++++++++++ 1 file changed, 125 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/zte,zx279128s-gmac.yaml diff --git a/Documentation/devicetree/bindings/net/zte,zx279128s-gmac.yaml b/Documentation/devicetree/bindings/net/zte,zx279128s-gmac.yaml new file mode 100644 index 0000000000..fcbdbafa76 --- /dev/null +++ b/Documentation/devicetree/bindings/net/zte,zx279128s-gmac.yaml @@ -0,0 +1,125 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/zte,zx279128s-gmac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ZTE zx279128s Ethernet switch + +maintainers: + - Navid Ghahremani + +description: + The ZTE zx279128s has a five-port gigabit Ethernet switch with a traffic + manager, a buffer manager and a DMA engine that connects it to the CPU. + Each port is described by a child node of ethernet-ports and becomes its + own network interface, with the MAC address given in that node. + +properties: + compatible: + const: zte,zx279128s-gmac + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + description: The traffic manager's interrupt, which signals frames + received for the CPU. + + ethernet-ports: + type: object + additionalProperties: false + + properties: + '#address-cells': + const: 1 + '#size-cells': + const: 0 + + patternProperties: + "^port@[0-4]$": + type: object + $ref: /schemas/net/ethernet-controller.yaml# + unevaluatedProperties: false + + properties: + reg: + description: Switch port number + maximum: 4 + + label: true + + phy-handle: true + + phy-mode: + description: internal for the SoC's own PHYs of ports 0-3, gmii + for an external PHY. + enum: [gmii, internal] + + required: + - reg + - phy-handle + - phy-mode + + required: + - '#address-cells' + - '#size-cells' + +required: + - compatible + - reg + - interrupts + - ethernet-ports + +additionalProperties: false + +examples: + - | + #include + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy8: ethernet-phy@8 { + reg = <8>; + }; + + phy10: ethernet-phy@a { + reg = <10>; + }; + }; + + macaddr: nvmem { + #nvmem-cell-cells = <1>; + }; + + ethernet@92000000 { + compatible = "zte,zx279128s-gmac"; + reg = <0x92000000 0x400000>; + interrupts = ; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + phy-handle = <&phy10>; + phy-mode = "internal"; + nvmem-cells = <&macaddr 0>; + nvmem-cell-names = "mac-address"; + }; + + port@4 { + reg = <4>; + label = "wan"; + phy-handle = <&phy8>; + phy-mode = "gmii"; + nvmem-cells = <&macaddr 1>; + nvmem-cell-names = "mac-address"; + }; + }; + }; -- 2.55.0