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Wed, 14 Oct 2026 00:23:16 -0700 (PDT) Received: from navid-pc ([2a01:4b00:a856:6220::a11]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48de3f7f8b8sm8500933f8f.35.2026.10.14.00.23.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Oct 2026 00:23:15 -0700 (PDT) From: Navid Ghahremani To: linux-arm-kernel@lists.infradead.org Cc: arnd@arndb.de, stefandoesinger@gmail.com, krzk@kernel.org, Navid Ghahremani , Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 21/24] dt-bindings: usb: Add ZTE ZX279128S DWC3 controller Date: Wed, 14 Oct 2026 08:21:01 +0100 Message-ID: <20261014072109.1759502-22-ghahramani.navid@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261014072109.1759502-1-ghahramani.navid@gmail.com> References: <20261014072109.1759502-1-ghahramani.navid@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Describe the USB host integration with three CRM clocks and four reset bits. Signed-off-by: Navid Ghahremani --- .../bindings/usb/zte,zx279128s-dwc3.yaml | 76 +++++++++++++++++++ 1 file changed, 76 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/zte,zx279128s-dwc3.yaml diff --git a/Documentation/devicetree/bindings/usb/zte,zx279128s-dwc3.yaml b/Documentation/devicetree/bindings/usb/zte,zx279128s-dwc3.yaml new file mode 100644 index 0000000000..2fd9fe0cc7 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/zte,zx279128s-dwc3.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/zte,zx279128s-dwc3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ZTE zx279128s DWC3 USB controller + +maintainers: + - Navid Ghahremani + +description: + The ZTE zx279128s has a DesignWare USB3 controller (DWC_usb3 2.80a) with + integrated USB 2.0 and USB 3.0 PHYs, used as a host. Its clocks and resets + come from the top clock and reset module. + +allOf: + - $ref: snps,dwc3-common.yaml# + +properties: + compatible: + const: zte,zx279128s-dwc3 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: 20 MHz reference clock + - description: bus (AXI) clock + - description: 32.768 kHz suspend clock + + clock-names: + items: + - const: ref + - const: bus_early + - const: suspend + + resets: + description: The four reset bits of the controller and its PHYs, in the + order they are released. + minItems: 4 + maxItems: 4 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + +unevaluatedProperties: false + +examples: + - | + #include + #include + + usb@9100000 { + compatible = "zte,zx279128s-dwc3"; + reg = <0x09100000 0x100000>; + interrupts = ; + clocks = <&topcrm ZX279128S_TOP_USB_REF>, + <&topcrm ZX279128S_TOP_USB_ACLK>, + <&topcrm ZX279128S_TOP_USB_SUSPEND>; + clock-names = "ref", "bus_early", "suspend"; + resets = <&topcrm ZX279128S_TOP_RST_USB_B11>, + <&topcrm ZX279128S_TOP_RST_USB_B14>, + <&topcrm ZX279128S_TOP_RST_USB_B9>, + <&topcrm ZX279128S_TOP_RST_USB_B10>; + dr_mode = "host"; + }; -- 2.55.0