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Wed, 14 Oct 2026 00:22:54 -0700 (PDT) Received: from navid-pc ([2a01:4b00:a856:6220::a11]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48de3f7f8b8sm8500933f8f.35.2026.10.14.00.22.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Oct 2026 00:22:54 -0700 (PDT) From: Navid Ghahremani To: linux-arm-kernel@lists.infradead.org Cc: arnd@arndb.de, stefandoesinger@gmail.com, krzk@kernel.org, Navid Ghahremani , Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 05/24] dt-bindings: reset: Add ZTE ZX279128S reset controller bindings Date: Wed, 14 Oct 2026 08:20:45 +0100 Message-ID: <20261014072109.1759502-6-ghahramani.navid@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261014072109.1759502-1-ghahramani.navid@gmail.com> References: <20261014072109.1759502-1-ghahramani.navid@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Define logical reset indices (0, 1, 2...) for the topcrm and crm2 reset controllers on ZTE ZX279128S SoCs. Signed-off-by: Navid Ghahremani --- .../dt-bindings/reset/zte,zx279128s-reset.h | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 include/dt-bindings/reset/zte,zx279128s-reset.h diff --git a/include/dt-bindings/reset/zte,zx279128s-reset.h b/include/dt-bindings/reset/zte,zx279128s-reset.h new file mode 100644 index 0000000000..5b580bcda8 --- /dev/null +++ b/include/dt-bindings/reset/zte,zx279128s-reset.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2026 Navid Ghahremani + */ + +#ifndef _DT_BINDINGS_RESET_ZTE_ZX279128S_RESET_H +#define _DT_BINDINGS_RESET_ZTE_ZX279128S_RESET_H + +/* + * Top CRM logical reset lines. Mapped by drivers/clk/zte/clk-zx279128s.c + * to hardware register offsets and bit shifts. + */ +#define ZX279128S_RESET_USB_B9 0 +#define ZX279128S_RESET_USB_B10 1 +#define ZX279128S_RESET_USB_B11 2 +#define ZX279128S_RESET_USB_B14 3 +#define ZX279128S_RESET_COUNT 4 + +/* + * Top CRM 2 logical reset lines. + */ +#define ZX279128S_CRM2_RESET_PCIE0 0 +#define ZX279128S_CRM2_RESET_PCIE1 1 +#define ZX279128S_CRM2_RESET_COUNT 2 + +#endif -- 2.55.0