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Wed, 14 Oct 2026 00:22:59 -0700 (PDT) Received: from navid-pc ([2a01:4b00:a856:6220::a11]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48de3f7f8b8sm8500933f8f.35.2026.10.14.00.22.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Oct 2026 00:22:58 -0700 (PDT) From: Navid Ghahremani To: linux-arm-kernel@lists.infradead.org Cc: arnd@arndb.de, stefandoesinger@gmail.com, krzk@kernel.org, Navid Ghahremani , Linus Walleij , Bartosz Golaszewski , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org Subject: [PATCH v2 08/24] gpio: Add ZTE ZX279128S GPIO driver Date: Wed, 14 Oct 2026 08:20:48 +0100 Message-ID: <20261014072109.1759502-9-ghahramani.navid@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261014072109.1759502-1-ghahramani.navid@gmail.com> References: <20261014072109.1759502-1-ghahramani.navid@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Expose the six banks using the generic GPIO implementation and enable the register clock before accessing the bank. Signed-off-by: Navid Ghahremani --- drivers/gpio/Kconfig | 12 ++++++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-zx279128s.c | 79 +++++++++++++++++++++++++++++++++++ 3 files changed, 92 insertions(+) create mode 100644 drivers/gpio/gpio-zx279128s.c diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index a48586bb8e..3ae51a3c10 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -902,6 +902,18 @@ config GPIO_ZEVIO help Say yes here to support the GPIO controller in LSI ZEVIO SoCs. +config GPIO_ZX279128S + tristate "ZTE zx279128s GPIO support" + depends on ARCH_ZTE || COMPILE_TEST + select GPIO_GENERIC + help + Say yes here to support the GPIO controller of the ZTE zx279128s + SoC. It has several banks of 16 lines each, which boards such as + the ZTE ZXHN H3600 use for LEDs, buttons and reset lines. + + To compile this driver as a module, choose M here: the module + will be called gpio-zx279128s. + config GPIO_ZYNQ tristate "Xilinx Zynq GPIO support" depends on ARCH_ZYNQ || ARCH_ZYNQMP || COMPILE_TEST diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index dc9e6d643b..a57ed7ec71 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -223,5 +223,6 @@ obj-$(CONFIG_GPIO_XLP) += gpio-xlp.o obj-$(CONFIG_GPIO_XRA1403) += gpio-xra1403.o obj-$(CONFIG_GPIO_XTENSA) += gpio-xtensa.o obj-$(CONFIG_GPIO_ZEVIO) += gpio-zevio.o +obj-$(CONFIG_GPIO_ZX279128S) += gpio-zx279128s.o obj-$(CONFIG_GPIO_ZYNQ) += gpio-zynq.o obj-$(CONFIG_GPIO_ZYNQMP_MODEPIN) += gpio-zynqmp-modepin.o diff --git a/drivers/gpio/gpio-zx279128s.c b/drivers/gpio/gpio-zx279128s.c new file mode 100644 index 0000000000..71eb6b5d82 --- /dev/null +++ b/drivers/gpio/gpio-zx279128s.c @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * ZTE zx279128s GPIO controller + * + * Copyright (C) 2026 Navid Ghahremani + */ + +#include +#include +#include +#include +#include +#include + +/* + * Each bank has 16 lines, one bit per line in each register. The registers + * at 0x04-0x10 and 0x28-0x34 control the interrupts, which are not supported + * yet. + */ +#define ZX279128S_GPIO_DIR 0x00 /* 1: output */ +#define ZX279128S_GPIO_DATA 0x14 /* line level */ +#define ZX279128S_GPIO_SET 0x18 /* write 1: drive high */ +#define ZX279128S_GPIO_CLEAR 0x1c /* write 1: drive low */ + +static int zx279128s_gpio_probe(struct platform_device *pdev) +{ + struct gpio_generic_chip_config config = { }; + struct device *dev = &pdev->dev; + struct gpio_generic_chip *chip; + void __iomem *base; + struct clk *clk; + int ret; + + chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); + if (!chip) + return -ENOMEM; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + clk = devm_clk_get_enabled(dev, NULL); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), "failed to get the clock\n"); + + config.dev = dev; + config.sz = 4; + config.dat = base + ZX279128S_GPIO_DATA; + config.set = base + ZX279128S_GPIO_SET; + config.clr = base + ZX279128S_GPIO_CLEAR; + config.dirout = base + ZX279128S_GPIO_DIR; + + ret = gpio_generic_chip_init(chip, &config); + if (ret) + return dev_err_probe(dev, ret, "failed to set up the GPIO chip\n"); + + chip->gc.ngpio = 16; + + return devm_gpiochip_add_data(dev, &chip->gc, NULL); +} + +static const struct of_device_id zx279128s_gpio_of_match[] = { + { .compatible = "zte,zx279128s-gpio" }, + { } +}; +MODULE_DEVICE_TABLE(of, zx279128s_gpio_of_match); + +static struct platform_driver zx279128s_gpio_driver = { + .probe = zx279128s_gpio_probe, + .driver = { + .name = "zx279128s-gpio", + .of_match_table = zx279128s_gpio_of_match, + }, +}; +module_platform_driver(zx279128s_gpio_driver); + +MODULE_AUTHOR("Navid Ghahremani "); +MODULE_DESCRIPTION("ZTE zx279128s GPIO controller driver"); +MODULE_LICENSE("GPL"); -- 2.55.0