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Wed, 14 Oct 2026 00:32:33 -0700 (PDT) Received: from localhost.localdomain ([2a06:c701:4778:c500:9cb0:7d9f:2fd:3903]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48de0967bf5sm9622415f8f.5.2026.10.14.00.32.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Oct 2026 00:32:32 -0700 (PDT) From: Avi Weiss To: Kenneth Feng , Alex Deucher Cc: =?UTF-8?q?Christian=20K=C3=B6nig?= , Lijo Lazar , amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Avi Weiss Subject: [PATCH] drm/amd/pm: propagate errors when forcing SMU11 clock levels Date: Wed, 14 Oct 2026 10:32:28 +0300 Message-ID: <20261014073228.2095339-1-thnkslprpt@gmail.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit navi10_force_clk_levels() and sienna_cichlid_force_clk_levels() return success when a DPM frequency lookup or soft frequency range update fails. smu_force_smuclk_levels() then records the requested clock mask even though the operation failed. Return the helper error from both callbacks instead to improve observability. No obvious reason to clobber the return values here. Fixes: db439ca21b81f ("drm/amd/powerplay: add function force_clk_levels for navi10") Fixes: b455159c05313 ("drm/amdgpu/powerplay: add initial swSMU support for sienna_cichlid (v2)") Signed-off-by: Avi Weiss --- drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 6 +++--- drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c index f8ca5eb9adc6..2d05088619f6 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c @@ -1439,15 +1439,15 @@ static int navi10_force_clk_levels(struct smu_context *smu, ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq); if (ret) - return 0; + return ret; ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq); if (ret) - return 0; + return ret; ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq, false); if (ret) - return 0; + return ret; break; case SMU_DCEFCLK: dev_info(smu->adev->dev, "Setting DCEFCLK min/max dpm level is not supported!\n"); diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c index b42897e7c066..4ef3863fae1a 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c @@ -1460,7 +1460,7 @@ static int sienna_cichlid_force_clk_levels(struct smu_context *smu, } forec_level_out: - return 0; + return ret; } static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu) base-commit: 4056b3c9d3c92ea45955641dbafeb9b960e146ef -- 2.43.0