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Document their compatible strings and describe the list of pins and functions that they provide. Signed-off-by: Prathamesh Shete Signed-off-by: Prateek Agarwal --- .../pinctrl/nvidia,tegra268-pinmux-aon.yaml | 78 ++++++++++ .../nvidia,tegra268-pinmux-common.yaml | 72 ++++++++++ .../pinctrl/nvidia,tegra268-pinmux-main.yaml | 136 ++++++++++++++++++ .../pinctrl/nvidia,tegra268-pinmux-uphy.yaml | 75 ++++++++++ 4 files changed, 361 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra268-pinmux-aon.yaml create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra268-pinmux-common.yaml create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra268-pinmux-main.yaml create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra268-pinmux-uphy.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra268-pinmux-aon.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra268-pinmux-aon.yaml new file mode 100644 index 000000000000..0757e15c1327 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra268-pinmux-aon.yaml @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra268-pinmux-aon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra268 AON Pinmux Controller + +maintainers: + - Thierry Reding + - Jon Hunter + +properties: + compatible: + const: nvidia,tegra268-pinmux-aon + + reg: + maxItems: 1 + +patternProperties: + "^pinmux(-[a-z0-9-]+)?$": + type: object + + # pin groups + additionalProperties: + $ref: nvidia,tegra268-pinmux-common.yaml + + properties: + nvidia,pins: + items: + enum: [ soc_gpio00_paa0, vcomp_alert_paa1, ao_retention_n_paa2, + batt_oc_paa3, bootv_ctl_n_paa4, power_on_paa5, + hdmi_cec_paa6, soc_gpio07_paa7, soc_gpio08_pbb0, + soc_gpio09_pbb1, gen2_i2c_scl_pcc0, gen2_i2c_sda_pcc1, + gen3_i2c_scl_pcc2, gen3_i2c_sda_pcc3, gp_pwm4_pcc4, + uart0_tx_pcc5, uart0_rx_pcc6, spi2_sck_pcc7, + spi2_miso_pdd0, spi2_mosi_pdd1, spi2_cs0_n_pdd2, + soc_gpio21_pdd3, soc_gpio23_pdd5, soc_gpio24_pdd6, + soc_gpio25_pdd7, soc_gpio26_pee0, soc_gpio27_pee1, + drive_ao_retention_n_paa2, drive_batt_oc_paa3, + drive_power_on_paa5, drive_vcomp_alert_paa1, + drive_bootv_ctl_n_paa4, drive_soc_gpio00_paa0, + drive_soc_gpio07_paa7, drive_soc_gpio08_pbb0, + drive_soc_gpio09_pbb1, drive_hdmi_cec_paa6, + drive_gen2_i2c_scl_pcc0, drive_gen2_i2c_sda_pcc1, + drive_gen3_i2c_scl_pcc2, drive_gen3_i2c_sda_pcc3, + drive_gp_pwm4_pcc4, drive_uart0_tx_pcc5, + drive_uart0_rx_pcc6, drive_spi2_sck_pcc7, + drive_spi2_miso_pdd0, drive_spi2_mosi_pdd1, + drive_spi2_cs0_n_pdd2, drive_soc_gpio21_pdd3, + drive_soc_gpio23_pdd5, drive_soc_gpio24_pdd6, + drive_soc_gpio25_pdd7, drive_soc_gpio26_pee0, + drive_soc_gpio27_pee1 ] + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + + pinmux@c7a2000 { + compatible = "nvidia,tegra268-pinmux-aon"; + reg = <0xc7a2000 0x2000>; + + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux-default { + uart0 { + nvidia,pins = "uart0_tx_pcc5"; + nvidia,function = "uarta_txd"; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra268-pinmux-common.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra268-pinmux-common.yaml new file mode 100644 index 000000000000..1b276a211b02 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra268-pinmux-common.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra268-pinmux-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra268 Pinmux Common Properties + +maintainers: + - Thierry Reding + - Jon Hunter + +$ref: nvidia,tegra-pinmux-common.yaml + +properties: + nvidia,function: + enum: [ dca_vsync, dca_hsync, rsvd0, dp_aux_ch0_hpd, dp_aux_ch1_hpd, + gp_pwm2, gp_pwm3, i2c7_clk, i2c7_dat, i2c9_clk, i2c9_dat, spi3_cs0, + spi3_cs3, spi3_din, spi3_dout, spi3_sck, uartf_cts, uartf_rts, + uartf_rxd, uartf_txd, spi1_cs0, spi1_cs1, spi1_din, spi1_dout, + spi1_sck, extperiph2_clk, extperiph1_clk, i2c12_clk, i2c12_dat, + nv_therm_fan_tach0, gp_pwm9, i2c0_clk, i2c0_dat, i2c1_clk, i2c1_dat, + i2s2_lrck, i2s2_sclk, i2s2_sdata_out, i2s2_sdata_in, uarte_cts, + uarte_rts, uarte_rxd, uarte_txd, i2c5_dat, i2c5_clk, i2s4_sdata_out, + i2s4_sclk, i2s4_sdata_in, i2s4_lrck, aud_mclk, i2s1_sclk, + i2s1_sdata_in, i2s1_sdata_out, i2s1_lrck, i2c11_clk, i2c11_dat, + xhalt_trig, gp_pwm1, gp_pwm6, gp_pwm7, gp_pwm8, ufs0, pe1_clkreq_l, + pe1_rst_l, pe2_rst_l, pe2_clkreq_l, pe3_clkreq_l, pe3_rst_l, + sgmii0_sma_mdio, sgmii0_sma_mdc, usb_vbus_en0, usb_vbus_en1, + pe4_clkreq_l, pe4_rst_l, eth0_mdio, eth0_mdc, eth2_mdio, eth2_mdc, + qspi0_cs_n, qspi0_io0, qspi0_io1, qspi0_io2, qspi0_io3, qspi0_sck, + dcb_vsync, dcb_hsync, dsa_lspii, dce_vsync, dce_hsync, bl_en, + bl_pwm_dim0, rsvd1, soc_therm_oc3, i2s5_sclk, i2s5_sdata_in, + extperiph3_clk, extperiph4_clk, i2s5_sdata_out, i2s5_lrck, + i2c14_dat, i2s8_sclk, i2s8_sdata_out, i2s8_lrck, i2c16_clk, + i2c16_dat, i2s3_sclk, i2s3_sdata_out, i2s3_sdata_in, i2s3_lrck, + pm_trig1, pm_trig0, dcc_vsync, dcc_hsync, rsvd2, dcf_vsync, + dcf_hsync, soundwire1_clk, soundwire1_dat0, soundwire1_dat1, + soundwire1_dat2, dmic2_clk, dmic2_dat, nv_therm_fan_tach1, + i2c15_clk, i2c15_dat, i2s7_sdata_out, dmic1_clk, dcd_vsync, + dcd_hsync, rsvd3, dcg_vsync, dcg_hsync, dspk1_clk, dspk1_dat, + soc_therm_oc2, istctrl_ist_done_n, soc_therm_oc1, tsc_edge_out0c, + tsc_edge_out0d, tsc_edge_out0a, tsc_edge_out0b, touch_clk, hdmi_cec, + i2c2_clk, i2c2_dat, i2c3_clk, i2c3_dat, gp_pwm4, uarta_txd, + uarta_rxd, spi2_sck, spi2_din, spi2_dout, spi2_cs0, tsc_sync1, + tsc_edge_out3, tsc_edge_out0, tsc_edge_out1, tsc_sync0, + soundwire0_clk, soundwire0_dat0, uartl_txd, uartl_rxd, i2s9_sclk, + i2s9_sdata_out, i2s9_sdata_in, i2s9_lrck, dmic5_dat, tsc_edge_out2 ] + + # out of the common properties, only these are allowed for Tegra268 + nvidia,pins: true + nvidia,pull: true + nvidia,tristate: true + nvidia,schmitt: true + nvidia,enable-input: true + nvidia,open-drain: true + nvidia,lock: true + nvidia,drive-type: true + nvidia,io-hv: true + +required: + - nvidia,pins + +# We would typically use unevaluatedProperties here but that has the +# downside that all the properties in the common bindings become valid +# for all chip generations. In this case, however, we want the per-SoC +# bindings to be able to override which of the common properties are +# allowed, since not all pinmux generations support the same sets of +# properties. This way, the common bindings define the format of the +# properties but the per-SoC bindings define which of them apply to a +# given chip. +additionalProperties: false diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra268-pinmux-main.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra268-pinmux-main.yaml new file mode 100644 index 000000000000..d195b7c5d169 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra268-pinmux-main.yaml @@ -0,0 +1,136 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra268-pinmux-main.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra268 Main Pinmux Controller + +maintainers: + - Thierry Reding + - Jon Hunter + +properties: + compatible: + const: nvidia,tegra268-pinmux-main + + reg: + maxItems: 1 + +patternProperties: + "^pinmux(-[a-z0-9-]+)?$": + type: object + + # pin groups + additionalProperties: + $ref: nvidia,tegra268-pinmux-common.yaml + + properties: + nvidia,pins: + items: + enum: [ soc_gpio250_pf0, soc_gpio251_pf1, soc_gpio252_pf2, + dp_aux_ch0_hpd_pf3, dp_aux_ch1_hpd_pf4, pwm2_pf7, pwm3_pg0, + gen7_i2c_scl_pg1, gen7_i2c_sda_pg2, gen9_i2c_scl_pg3, + gen9_i2c_sda_pg4, soc_gpio124_pl0, soc_gpio125_pl1, + fan_tach0_pl2, soc_gpio127_pl3, soc_gpio128_pl4, + soc_gpio129_pl5, soc_gpio130_pl6, soc_gpio131_pl7, + gp_pwm9_pm0, soc_gpio133_pm1, soc_gpio178_pv0, + uart4_tx_pv2, uart4_rx_pv3, uart4_rts_n_pv4, + uart4_cts_n_pv5, dap2_clk_pv6, dap2_fs_pw1, + gen1_i2c_scl_pw2, gen1_i2c_sda_pw3, gen0_i2c_scl_pw4, + gen0_i2c_sda_pw5, pwr_i2c_scl_pw6, pwr_i2c_sda_pw7, + soc_gpio139_pp1, dap4_sclk_pp6, dap4_dout_pp7, + dap4_din_pq0, dap4_fs_pq1, soc_gpio152_pq6, + soc_gpio153_pq7, aud_mclk_pr0, soc_gpio155_pr1, + dap1_sclk_pr2, dap1_out_pr3, dap1_in_pr4, dap1_fs_pr5, + gen11_i2c_scl_pr6, gen11_i2c_sda_pr7, soc_gpio351_ps1, + qspi0_sck_pt0, qspi0_cs_n_pt1, qspi0_io0_pt2, + qspi0_io1_pt3, qspi0_io2_pt4, qspi0_io3_pt5, + soc_gpio192_pt6, soc_gpio270_py0, soc_gpio271_py1, + soc_gpio272_py2, soc_gpio273_py3, soc_gpio274_py4, + soc_gpio275_py5, soc_gpio276_py6, soc_gpio277_py7, + soc_gpio278_pz0, soc_gpio279_pz1, xhalt_trig_pz2, + soc_gpio281_pz3, soc_gpio282_pz4, soc_gpio283_pz5, + soc_gpio284_pz6, soc_gpio285_pz7, soc_gpio286_pal0, + soc_gpio287_pal1, soc_gpio288_pal2, cpu_pwr_req_ph0, + gpu_pwr_req_ph1, spi3_sck_ph6, spi3_miso_ph7, + spi3_mosi_pj0, spi3_cs0_pj1, spi3_cs3_pj2, uart5_tx_pj3, + uart5_rx_pj4, uart5_rts_n_pj5, uart5_cts_n_pj6, + spi1_sck_pj7, spi1_miso_pk0, spi1_mosi_pk1, spi1_cs0_pk2, + spi1_cs1_pk3, extperiph1_clk_pk4, extperiph2_clk_pk5, + gen12_i2c_scl_pk6, gen12_i2c_sda_pk7, + drive_cpu_pwr_req_ph0, drive_gpu_pwr_req_ph1, + drive_spi3_cs0_pj1, drive_spi3_cs3_pj2, + drive_spi3_miso_ph7, drive_spi3_mosi_pj0, + drive_spi3_sck_ph6, drive_uart5_cts_n_pj6, + drive_uart5_rts_n_pj5, drive_uart5_rx_pj4, + drive_uart5_tx_pj3, drive_spi1_cs0_pk2, drive_spi1_cs1_pk3, + drive_spi1_miso_pk0, drive_spi1_mosi_pk1, + drive_spi1_sck_pj7, drive_extperiph2_clk_pk5, + drive_extperiph1_clk_pk4, drive_gen12_i2c_scl_pk6, + drive_gen12_i2c_sda_pk7, drive_soc_gpio124_pl0, + drive_soc_gpio125_pl1, drive_fan_tach0_pl2, + drive_soc_gpio127_pl3, drive_soc_gpio128_pl4, + drive_soc_gpio129_pl5, drive_soc_gpio130_pl6, + drive_soc_gpio131_pl7, drive_gp_pwm9_pm0, + drive_soc_gpio133_pm1, drive_qspi0_cs_n_pt1, + drive_qspi0_io0_pt2, drive_qspi0_io1_pt3, + drive_qspi0_io2_pt4, drive_qspi0_io3_pt5, + drive_qspi0_sck_pt0, drive_soc_gpio192_pt6, + drive_soc_gpio139_pp1, drive_dap4_dout_pp7, + drive_dap4_sclk_pp6, drive_dap4_din_pq0, drive_dap4_fs_pq1, + drive_soc_gpio152_pq6, drive_soc_gpio153_pq7, + drive_soc_gpio155_pr1, drive_aud_mclk_pr0, + drive_dap1_sclk_pr2, drive_dap1_in_pr4, drive_dap1_out_pr3, + drive_dap1_fs_pr5, drive_gen11_i2c_scl_pr6, + drive_gen11_i2c_sda_pr7, drive_soc_gpio351_ps1, + drive_gen0_i2c_scl_pw4, drive_gen0_i2c_sda_pw5, + drive_gen1_i2c_scl_pw2, drive_gen1_i2c_sda_pw3, + drive_dap2_fs_pw1, drive_dap2_clk_pv6, + drive_soc_gpio178_pv0, drive_uart4_cts_n_pv5, + drive_uart4_rts_n_pv4, drive_uart4_rx_pv3, + drive_uart4_tx_pv2, drive_pwr_i2c_sda_pw7, + drive_pwr_i2c_scl_pw6, drive_soc_gpio250_pf0, + drive_soc_gpio251_pf1, drive_soc_gpio252_pf2, + drive_dp_aux_ch0_hpd_pf3, drive_dp_aux_ch1_hpd_pf4, + drive_pwm2_pf7, drive_pwm3_pg0, drive_gen7_i2c_scl_pg1, + drive_gen7_i2c_sda_pg2, drive_gen9_i2c_scl_pg3, + drive_gen9_i2c_sda_pg4, drive_soc_gpio270_py0, + drive_soc_gpio271_py1, drive_soc_gpio272_py2, + drive_soc_gpio273_py3, drive_soc_gpio274_py4, + drive_soc_gpio275_py5, drive_soc_gpio276_py6, + drive_soc_gpio277_py7, drive_soc_gpio278_pz0, + drive_soc_gpio279_pz1, drive_soc_gpio282_pz4, + drive_soc_gpio283_pz5, drive_soc_gpio284_pz6, + drive_soc_gpio285_pz7, drive_soc_gpio286_pal0, + drive_soc_gpio287_pal1, drive_soc_gpio288_pal2, + drive_xhalt_trig_pz2, drive_soc_gpio281_pz3, dap2_din_pw0, + dap2_dout_pv7, drive_dap2_din_pw0, drive_dap2_dout_pv7 ] + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + + pinmux@c281000 { + compatible = "nvidia,tegra268-pinmux-main"; + reg = <0xc281000 0xc000>; + + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux-default { + spi3-cs0 { + nvidia,pins = "spi3_cs0_pj1"; + nvidia,function = "spi3_cs0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra268-pinmux-uphy.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra268-pinmux-uphy.yaml new file mode 100644 index 000000000000..0a3bb45a512a --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra268-pinmux-uphy.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra268-pinmux-uphy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra268 UPHY Pinmux Controller + +maintainers: + - Thierry Reding + - Jon Hunter + +properties: + compatible: + const: nvidia,tegra268-pinmux-uphy + + reg: + maxItems: 1 + +patternProperties: + "^pinmux(-[a-z0-9-]+)?$": + type: object + + # pin groups + additionalProperties: + $ref: nvidia,tegra268-pinmux-common.yaml + + properties: + nvidia,pins: + items: + enum: [ pex_l4_clkreq_n_pd0, pex_l4_rst_n_pd1, eth0_mdio_pd4, + eth0_mdc_pd5, eth2_mdio_pe2, eth2_mdc_pe3, + pex_l1_clkreq_n_pb0, pex_l1_rst_n_pb1, pex_wake_n_pc2, + pex_l2_rst_n_pb3, pex_l2_clkreq_n_pb2, pex_l3_clkreq_n_pb4, + pex_l3_rst_n_pb5, sgmii0_sma_mdio_pc0, sgmii0_sma_mdc_pc1, + soc_gpio113_pb6, soc_gpio114_pb7, pwm1_pa0, pwm6_pa1, + pwm7_pa2, pwm8_pa3, ufs0_ref_clk_pa4, ufs0_rst_n_pa5, + drive_pex_l4_clkreq_n_pd0, drive_pex_l4_rst_n_pd1, + drive_eth0_mdio_pd4, drive_eth0_mdc_pd5, + drive_eth2_mdio_pe2, drive_eth2_mdc_pe3, + drive_pex_l1_clkreq_n_pb0, drive_pex_l1_rst_n_pb1, + drive_pex_wake_n_pc2, drive_pex_l2_rst_n_pb3, + drive_pex_l2_clkreq_n_pb2, drive_pex_l3_clkreq_n_pb4, + drive_pex_l3_rst_n_pb5, drive_sgmii0_sma_mdio_pc0, + drive_sgmii0_sma_mdc_pc1, drive_soc_gpio113_pb6, + drive_soc_gpio114_pb7, drive_pwm1_pa0, drive_pwm6_pa1, + drive_pwm7_pa2, drive_pwm8_pa3, drive_ufs0_ref_clk_pa4, + drive_ufs0_rst_n_pa5 ] + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + + pinmux@82e0000 { + compatible = "nvidia,tegra268-pinmux-uphy"; + reg = <0x82e0000 0x4000>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_default>; + + pinmux_default: pinmux-default { + pex { + nvidia,pins = "pex_l1_rst_n_pb1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + }; -- 2.17.1