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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb08.amd.com; pr=C Received: from satlexmb08.amd.com (165.204.84.17) by SJ5PEPF000001E9.mail.protection.outlook.com (10.167.242.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.522.6 via Frontend Transport; Wed, 14 Oct 2026 21:34:30 +0000 Received: from satlexmb08.amd.com (10.181.42.217) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.53; Wed, 14 Oct 2026 16:34:23 -0500 Received: from xsjblevinsk51.xilinx.com (10.180.168.240) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server id 15.2.2562.53 via Frontend Transport; Wed, 14 Oct 2026 16:34:23 -0500 From: Ben Levinsky To: , , , , , CC: , , , , , , Subject: [PATCH 2/6] remoteproc: amd_mbv_bram: Restore reset GPIO direction after PL reconfig Date: Wed, 14 Oct 2026 14:34:22 -0700 Message-ID: <20261014213426.2957480-3-ben.levinsky@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20261014213426.2957480-1-ben.levinsky@amd.com> References: <20261014213426.2957480-1-ben.levinsky@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001E9:EE_|DSVPR12MB922022:EE_ X-MS-Office365-Filtering-Correlation-Id: 70935c7a-3ff2-4c8b-03a5-08df2a3aee34 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|7416014|36860700016|376014|1800799024|23010399003|6133799003|18002099003|22082099003|10067099003|3023799007|11063799006|261009223027099003|56012099006; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: jimatmGTUVwPS2040YeSga3Cucua4HNWIkz0FjDgS/sE1C9VH9Ag93ppTCIHzldXaS9akHP2Gih4fJvdVX0RLMfuCythzovDm55gFvd7oc/D3kg2dSpGTz8zay5KTlKtCEJo0qx/OCny8IKJxVFjz4xHe02llXSGnKTV8KUH66xOHbF00ozWXvHgDT47iKJvkydZof+3kjp7ZUCcgc+T/mS0QXjE1O/OWaj4o1krksIBsw44NTbZ78n0w3oOm6PB9QWj+4ZJQDwnzEIBoaI+8Xxh/riRCrYMNEBKVloP5nNB3Hxh1BUjOVuJ85rqEzRgkCL9ubW2Y77PfjoKDVK4JsXK9wmkOcAWvILcbENmYWmIuAt66/6jUhd6JBqn838tW8GsJ2dHRiT45mt1XDzcwxRE2+DdY1BWN9oDDTh3UuELLQ4vDbAytU51k1c6bz9P X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Oct 2026 21:34:30.2036 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 70935c7a-3ff2-4c8b-03a5-08df2a3aee34 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001E9.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DSVPR12MB922022 Partial reconfiguration of the programmable logic restores the AXI GPIO that drives the soft-core reset to its hardware default direction, but gpiolib keeps its cached output direction. gpiod_set_value_cansleep() then only updates the data register, so the processor never sees a reset transition: remoteproc reports it as running while the newly loaded firmware never starts. Use gpiod_direction_output() for every reset transition so the output direction is re-established, and assert reset briefly before releasing it so each start produces a clean reset pulse after the firmware has been loaded. Fixes: f87b4998994e ("remoteproc: Add AMD MicroBlaze/V BRAM-based remote processor driver") Assisted-by: LLM sparse Signed-off-by: Ben Levinsky --- drivers/remoteproc/amd_mbv_bram_rproc.c | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/drivers/remoteproc/amd_mbv_bram_rproc.c b/drivers/remoteproc/amd_mbv_bram_rproc.c index 6cf33c7b7e64..da621f62f7df 100644 --- a/drivers/remoteproc/amd_mbv_bram_rproc.c +++ b/drivers/remoteproc/amd_mbv_bram_rproc.c @@ -16,6 +16,7 @@ */ #include +#include #include #include #include @@ -94,8 +95,24 @@ static int amd_bram_rproc_start(struct rproc *rproc) return ret; } + /* + * Partial reconfiguration restores the PL GPIO hardware defaults but + * leaves gpiolib's cached direction unchanged. Re-establish the output + * direction and generate a reset pulse after firmware has been loaded. + * gpiod_set_value_cansleep() is insufficient here because it changes the + * value without restoring an output direction lost during DFX. + */ + ret = gpiod_direction_output(priv->reset, 1); + if (ret) { + dev_err(priv->dev, "failed to assert reset: %d\n", ret); + clk_disable_unprepare(priv->clk); + return ret; + } + /* Hold reset asserted long enough to provide a clean reset pulse. */ + usleep_range(10, 20); + /* Deassert reset and let the processor run. */ - ret = gpiod_set_value_cansleep(priv->reset, 0); + ret = gpiod_direction_output(priv->reset, 0); if (ret) { dev_err(priv->dev, "failed to deassert reset: %d\n", ret); clk_disable_unprepare(priv->clk); @@ -110,8 +127,8 @@ static int amd_bram_rproc_stop(struct rproc *rproc) struct amd_bram_rproc *priv = rproc->priv; int ret; - /* Assert reset before disabling the processor clock. */ - ret = gpiod_set_value_cansleep(priv->reset, 1); + /* Restore the output direction after DFX and assert reset. */ + ret = gpiod_direction_output(priv->reset, 1); if (ret) { dev_err(priv->dev, "failed to assert reset: %d\n", ret); return ret; -- 2.34.1