From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 578DC49E5E5; Thu, 15 Oct 2026 10:54:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1792061672; cv=none; b=m2LBB1AoHNiIYLpL5Ps4y31e2Z+Js+43X7FxbgL9UVu9HQZlaGScEiMFerIqBTT8kWXe9X6zejmISuwP6Iu6AH6GqyfWTOSswfx5a6qT1IBuw0hLuSnfJnArNDcXCA1FK3AlaHro8fWBrRW6vqYQ65GbIi501Q38NgbVdRUVOi4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1792061672; c=relaxed/simple; bh=jEiCuk+3TJFdVLdOVB6ZHGauBFtFVSE/sTByl3iEMT8=; h=From:Subject:Date:Message-Id:MIME-Version:Content-Type:To:Cc; b=gwvETDfHSis96xh74Y9bfyF919xXA3qf2WnvWzDffs8b0/a5vw804+gncbnDs4Kw5LClDGt4XjKC8Y0/wZvEq/5Wg9rmzHb5+vzxiTqlt7P/Gu25b6RGVWV26rPcG9OC7e67kEvB7wU1jFxtbyyvdAV0SkTISIBgpLQpIvJZJeI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=tD6W5Z9V; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="tD6W5Z9V" Received: by smtp.kernel.org (Postfix) with ESMTPS id E925CC2BCC7; Thu, 15 Oct 2026 10:54:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1792061672; bh=jEiCuk+3TJFdVLdOVB6ZHGauBFtFVSE/sTByl3iEMT8=; h=From:Subject:Date:To:Cc:Reply-To:From; b=tD6W5Z9V1nq1cpte8ibCeqnf4x3X4GqZs/+B8JgTMojAQYsR6IgKcler+Q9kpMrYL mwek3eT/hvBtGYXb1mezltk4iPPTL/hxekFzV74BUInOBoitW5tN3B8sJ9EI5gQeeE t92NHGpZJnxZtnQrd9dRTTSNxqzXwMEf1mu2Fb3wHFk5VWopVXHVz3KbgmEeUvqQFK 7evjck9Hcd206K3KAxLqpVXAI7/d3tMm3+3acaPze5ZoF6KQhByvNNvk6uaRAthsPq Xh+JNsuuom0Xm/qxWN81zZHa6tjdY82/+HSb8LRjqlUgN1ooSgfTaeMTBM4w4xsF9D Ri/K3EDRADbpw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id C2C9CCC6B34; Thu, 15 Oct 2026 10:54:31 +0000 (UTC) From: Long Zhao via B4 Relay Subject: [PATCH v10 0/8] gpio: add Ambarella CV75 PL061 support Date: Thu, 15 Oct 2026 18:53:27 +0800 Message-Id: <20261015-cv75-gpio-v10-0-3fe3eb315a55@ambarella.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAKew0GoC/zWNzQqDMBCEX0X23JRErT899T2Kh7iuukWNJDa0i O/eqBTmMsPHNys4skwO7tEKljw7NlMoSl4iwF5PHQluwgCxjDMlZS7Q5zfRzWxEkiRNjqppSSk I/Gyp5c8he1Znd+/6Rbjsgp3o2S3Gfo83X+7c36tOrw8phRRpkSHGRanTunjosdaWhkFf0YxQb dv2AwlV3aC3AAAA X-Change-ID: 20261007-cv75-gpio-333d7c1dfe11 To: Bartosz Golaszewski , linux-gpio@vger.kernel.org Cc: Linus Walleij , Michael Walle , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Krzysztof Kozlowski , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, Long Zhao , Long Zhao , linux-kernel@vger.kernel.org, Conor Dooley , Chanho Min X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1792061669; l=4253; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=jEiCuk+3TJFdVLdOVB6ZHGauBFtFVSE/sTByl3iEMT8=; b=zZjlJN80OIBIGXahxvQr1Z5/AlxIuearouUxyeqsRWMkYmwuvGmFDjCdsfwszdYo9dnUkmNGi Oa67TlKtf/jCxOsRZOsDw2NHKyF9mM9dZB655KNw0pIDxv6TkALbwUF X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com The ambarella vendor prefix [1] is applied in the devicetree tree. Do not apply the binding until the prefix reaches linux-next. The driver patches do not have that dependency. Please take this series through the GPIO tree. The quirk, the PL061 conversion and the Ambarella layout belong together. This is v10 of the GPIO patches from the combined CV75 series. The posting on Oct 9 numbered them v1 after the split. That was a mistake. These patches convert the ARM PL061 data path to regmap, then add the CV75 layout. GPIO data path uses gpio-regmap with two layouts (ARM PrimeCell and Ambarella). ARM PL061 sets GPIO_REGMAP_QUIRK_SET_AFTER_DIR. IRQ stays a custom PL061 irqchip. The linear domain is created with the PL061 private data and attached by gpio-regmap. regmap-irq is not used. Tested on the CV75 EVK. The board boots. gpio-hammer toggles gpiochip0 line 26 ten times, and gpio-event-mon on line 27 records ten alternating rising and falling edges. Changes since the combined v9 [2]: - dt-bindings: explain that CV75 is a modified PL061 (Conor). - gpio-regmap: move quirks after fixed_direction_output (Andy). - gpio: pl061: Andy's review on the regmap conversion and switch: use regmap_test_bits()/clear_bits()/set_bits()/assign_bits(), drop the redundant if (pending) and fast_io, introduce the ARM regmap_config (including REGCACHE_FLAT_S) in the convert patch and leave it there, blank line after guard() plus the blank-line and reverse Christmas tree cleanups, and keep the upstream pl061_irq_chip name and unsigned irq_type() trigger without adding .name. - gpio: pl061: cache DAT (REGCACHE_FLAT_S, not volatile) so gpio_set() does not read-modify-write the pin level (Sashiko). Changes since the Oct 9 GPIO posting [3]: - gpio: pl061: Andy's follow-ups since that posting: assign_bits for DAT writes, drop fast_io, name the ARM regmap_config in the convert patch, the guard()/blank-line/irq_type cleanups, and keep the upstream pl061_irq_chip name and unsigned trigger without adding .name. - gpiolib: regmap: add Michael Walle's Reviewed-by on GPIO_REGMAP_QUIRK_SET_AFTER_DIR. - gpio: pl061: restore Andy's and Linus's Reviewed-by on the Ambarella variant. [1] https://patch.msgid.link/20261014-cv75-prefix-v1-1-fe95ed567880@ambarella.com [2] https://patch.msgid.link/20261001-cv75-v5-v9-0-486cc289a4b8@ambarella.com [3] https://patch.msgid.link/20261009-cv75-gpio-v1-0-5836bd438423@ambarella.com To: Bartosz Golaszewski To: linux-gpio@vger.kernel.org Cc: Linus Walleij Cc: Michael Walle Cc: Andy Shevchenko Cc: Rob Herring Cc: Krzysztof Kozlowski Cc: Krzysztof Kozlowski Cc: Krzysztof Kozlowski Cc: Conor Dooley Cc: devicetree@vger.kernel.org Cc: Long Zhao Cc: Long Zhao Cc: linux-kernel@vger.kernel.org Assisted-by: LLM Signed-off-by: Long Zhao --- Long Zhao (8): dt-bindings: gpio: pl061: add Ambarella CV75 variant gpiolib: regmap: add GPIO_REGMAP_QUIRK_SET_AFTER_DIR gpio: pl061: drop redundant pending check in the IRQ handler gpio: pl061: convert register access to regmap gpio: pl061: use IRQ_TYPE_LEVEL_MASK and IRQ_TYPE_EDGE_BOTH gpio: pl061: use cleanup helpers for locks gpio: pl061: switch data path to gpio-regmap gpio: pl061: add Ambarella register-layout variant .../devicetree/bindings/gpio/pl061-gpio.yaml | 25 +- drivers/gpio/Kconfig | 2 + drivers/gpio/gpio-pl061.c | 552 +++++++++++++-------- drivers/gpio/gpio-regmap.c | 15 +- include/linux/amba/bus.h | 1 + include/linux/gpio/regmap.h | 14 + 6 files changed, 409 insertions(+), 200 deletions(-) --- base-commit: 34cf6dafc47441dfb6b356a095b89c3585a93714 change-id: 20261007-cv75-gpio-333d7c1dfe11 Best regards, -- Long Zhao