From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 579C94A7CA7; Thu, 15 Oct 2026 10:54:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1792061672; cv=none; b=pS6TU4UZbiSr5fB/0RTQXlCTytICto5cDx+CrzRkKhHhIJ+qXPcJo+cpEcq16/nAfp0M1/LvrAjXPmZFsM+D7dYC+/pz57NAaKZkA7lfZIGY6t0YkgZJ+Css2sn9pk16KNouGR/rmWp8+bkylugbwnVUf9QWpdyZ0YF23czE/HM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1792061672; c=relaxed/simple; bh=6qmV5fP/ovYkMChG07yhC6ChgksYfCJp8P8sxHcAz/c=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=KFnF/2JylgwAIEmDm3LX/wxmnVze51zIJdZqQxV09csD4gVWmKr73GnSJXHsNQuOAk6zufpzKC+IpCS1OThdDM/1r43T0/D3GljK2xc/GFdUGjYz5xWF/HV00RReWhMALC1p/7iIKXnrU1oO7QzCXe+4a96jDqpbr3TAF9z8VRM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=j7Ze7pQN; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="j7Ze7pQN" Received: by smtp.kernel.org (Postfix) with ESMTPS id 02BD2C2BCFB; Thu, 15 Oct 2026 10:54:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1792061672; bh=6qmV5fP/ovYkMChG07yhC6ChgksYfCJp8P8sxHcAz/c=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=j7Ze7pQNlea9bkUyFWzMJpZbjGh0BCw2S/t2xpGjeKoGuFYHlBp1WiXX7Zr04E2qV VLY/e9kQX/soMj09RIRRintCIvp8XWjSdcc3hsLh9HhSJxJMn/1drHWT43a2JPMoj/ YvqCpHuSt1rJMu6ARiWLBSV4WHVdLw1HHfPFdXhUmOI3IOFVb1YYdD+KG9+8W+hBAd 9LY2UGurfaevyhFjPKlgiANAwf971R7eFtgr0cz4uEJIcSQh7hEoRPCdT2rBYYPiVb bv5uZ3PR1RYyTsdfJHzMIURnoBCYIWVtMucTH5AqEEq6KGBR8vLwm83wZYb6PSFt3F Zt5kFYI8LLkoA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id D685ACC6B33; Thu, 15 Oct 2026 10:54:31 +0000 (UTC) From: Long Zhao via B4 Relay Date: Thu, 15 Oct 2026 18:53:28 +0800 Subject: [PATCH v10 1/8] dt-bindings: gpio: pl061: add Ambarella CV75 variant Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261015-cv75-gpio-v10-1-3fe3eb315a55@ambarella.com> References: <20261015-cv75-gpio-v10-0-3fe3eb315a55@ambarella.com> In-Reply-To: <20261015-cv75-gpio-v10-0-3fe3eb315a55@ambarella.com> To: Bartosz Golaszewski , linux-gpio@vger.kernel.org Cc: Linus Walleij , Michael Walle , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Krzysztof Kozlowski , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, Long Zhao , Long Zhao , linux-kernel@vger.kernel.org, Conor Dooley X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1792061669; l=2127; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=BkO6pO1YpBBieaeL0yXFXs09zVgjmaMwMQO7kuG29w4=; b=G4zLzsTlBcqQj1SoDIghxuZesERSzrNjhMPFY+NWXR4aiBhV5T+iGNhKyjUIZ2RtmI4euI1sO mE4LByiHHH8C5wM+wP5OaIVhMuKGsvkZNQaUiS8wIRiPHqn9rBgTpRF X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com From: Long Zhao The CV75 GPIO is a modified PL061. The basic registers have the same names and roles (DAT/DIR/IS/IBE/IEV/IE/MIS/IC). Each bank is 32-bit and 32 lines and adds MASK and ENABLE, so it is not register-compatible with the ARM PL061 and arm,pl061 must not be used as a fallback. The AMBA core matches the PL061 driver by PrimeCell ID, not by the DT compatible string. These blocks do not implement the standard PL061 ID (0x00041061) in the ID registers, so arm,primecell-periphid is required and is fixed to 0x000e8061; the driver uses that ID to select the Ambarella layout. gpio-ranges is required because each bank is a slice of the SoC pinctrl pin space. Acked-by: Conor Dooley Signed-off-by: Long Zhao --- .../devicetree/bindings/gpio/pl061-gpio.yaml | 25 +++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/gpio/pl061-gpio.yaml b/Documentation/devicetree/bindings/gpio/pl061-gpio.yaml index 4d970e55104b..c22dd8a1d2c1 100644 --- a/Documentation/devicetree/bindings/gpio/pl061-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/pl061-gpio.yaml @@ -15,7 +15,9 @@ select: properties: compatible: contains: - const: arm,pl061 + enum: + - arm,pl061 + - ambarella,cv75-gpio required: - compatible @@ -25,7 +27,9 @@ properties: compatible: items: - - const: arm,pl061 + - enum: + - ambarella,cv75-gpio + - arm,pl061 - const: arm,primecell reg: @@ -64,6 +68,21 @@ required: - "#gpio-cells" - gpio-controller -additionalProperties: false +allOf: + - $ref: /schemas/arm/primecell.yaml# + - if: + properties: + compatible: + contains: + const: ambarella,cv75-gpio + then: + properties: + arm,primecell-periphid: + const: 0x000e8061 + required: + - arm,primecell-periphid + - gpio-ranges + +unevaluatedProperties: false ... -- 2.34.1