From: Long Zhao via B4 Relay <devnull+longzhao.ambarella.com@kernel.org>
To: Bartosz Golaszewski <brgl@kernel.org>, linux-gpio@vger.kernel.org
Cc: Linus Walleij <linusw@kernel.org>,
Michael Walle <mwalle@kernel.org>,
Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>,
Conor Dooley <conor+dt@kernel.org>,
devicetree@vger.kernel.org, Long Zhao <longzhao@ambarella.com>,
Long Zhao <zl020895@163.com>,
linux-kernel@vger.kernel.org
Subject: [PATCH v10 6/8] gpio: pl061: use cleanup helpers for locks
Date: Thu, 15 Oct 2026 18:53:33 +0800 [thread overview]
Message-ID: <20261015-cv75-gpio-v10-6-3fe3eb315a55@ambarella.com> (raw)
In-Reply-To: <20261015-cv75-gpio-v10-0-3fe3eb315a55@ambarella.com>
From: Long Zhao <longzhao@ambarella.com>
Convert raw_spinlock critical sections to guard() from cleanup.h.
Reviewed-by: Linus Walleij <linusw@kernel.org>
Signed-off-by: Long Zhao <longzhao@ambarella.com>
---
drivers/gpio/gpio-pl061.c | 25 ++++++++++---------------
1 file changed, 10 insertions(+), 15 deletions(-)
diff --git a/drivers/gpio/gpio-pl061.c b/drivers/gpio/gpio-pl061.c
index 8f431d08573d..5c6d4209dc8e 100644
--- a/drivers/gpio/gpio-pl061.c
+++ b/drivers/gpio/gpio-pl061.c
@@ -10,6 +10,7 @@
*/
#include <linux/amba/bus.h>
#include <linux/bitops.h>
+#include <linux/cleanup.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/gpio/driver.h>
@@ -105,11 +106,10 @@ static int pl061_get_direction(struct gpio_chip *gc, unsigned offset)
static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
{
struct pl061 *pl061 = gpiochip_get_data(gc);
- unsigned long flags;
- raw_spin_lock_irqsave(&pl061->lock, flags);
+ guard(raw_spinlock_irqsave)(&pl061->lock);
+
regmap_clear_bits(pl061->regmap, GPIODIR, BIT(offset));
- raw_spin_unlock_irqrestore(&pl061->lock, flags);
return 0;
}
@@ -118,10 +118,10 @@ static int pl061_direction_output(struct gpio_chip *gc, unsigned offset,
int value)
{
struct pl061 *pl061 = gpiochip_get_data(gc);
- unsigned long flags;
unsigned int mask = BIT(offset);
- raw_spin_lock_irqsave(&pl061->lock, flags);
+ guard(raw_spinlock_irqsave)(&pl061->lock);
+
regmap_assign_bits(pl061->regmap, BIT(offset + PL061_DATA_OFFSET),
BIT(offset), value);
regmap_set_bits(pl061->regmap, GPIODIR, mask);
@@ -132,7 +132,6 @@ static int pl061_direction_output(struct gpio_chip *gc, unsigned offset,
*/
regmap_assign_bits(pl061->regmap, BIT(offset + PL061_DATA_OFFSET),
BIT(offset), value);
- raw_spin_unlock_irqrestore(&pl061->lock, flags);
return 0;
}
@@ -161,7 +160,6 @@ static int pl061_irq_type(struct irq_data *d, unsigned trigger)
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct pl061 *pl061 = gpiochip_get_data(gc);
int offset = irqd_to_hwirq(d);
- unsigned long flags;
unsigned int gpioiev = 0;
unsigned int gpioibe = 0;
unsigned int gpiois = 0;
@@ -178,8 +176,7 @@ static int pl061_irq_type(struct irq_data *d, unsigned trigger)
return -EINVAL;
}
-
- raw_spin_lock_irqsave(&pl061->lock, flags);
+ guard(raw_spinlock_irqsave)(&pl061->lock);
regmap_read(pl061->regmap, GPIOIEV, &gpioiev);
regmap_read(pl061->regmap, GPIOIS, &gpiois);
@@ -239,8 +236,6 @@ static int pl061_irq_type(struct irq_data *d, unsigned trigger)
regmap_write(pl061->regmap, GPIOIBE, gpioibe);
regmap_write(pl061->regmap, GPIOIEV, gpioiev);
- raw_spin_unlock_irqrestore(&pl061->lock, flags);
-
return 0;
}
@@ -270,9 +265,9 @@ static void pl061_irq_mask(struct irq_data *d)
struct pl061 *pl061 = gpiochip_get_data(gc);
u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
- raw_spin_lock(&pl061->lock);
+ guard(raw_spinlock)(&pl061->lock);
+
regmap_clear_bits(pl061->regmap, GPIOIE, mask);
- raw_spin_unlock(&pl061->lock);
gpiochip_disable_irq(gc, d->hwirq);
}
@@ -285,9 +280,9 @@ static void pl061_irq_unmask(struct irq_data *d)
gpiochip_enable_irq(gc, d->hwirq);
- raw_spin_lock(&pl061->lock);
+ guard(raw_spinlock)(&pl061->lock);
+
regmap_set_bits(pl061->regmap, GPIOIE, mask);
- raw_spin_unlock(&pl061->lock);
}
/**
--
2.34.1
next prev parent reply other threads:[~2026-10-15 10:54 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-15 10:53 [PATCH v10 0/8] gpio: add Ambarella CV75 PL061 support Long Zhao via B4 Relay
2026-10-15 10:53 ` [PATCH v10 1/8] dt-bindings: gpio: pl061: add Ambarella CV75 variant Long Zhao via B4 Relay
2026-10-16 13:24 ` Linus Walleij
2026-10-15 10:53 ` [PATCH v10 2/8] gpiolib: regmap: add GPIO_REGMAP_QUIRK_SET_AFTER_DIR Long Zhao via B4 Relay
2026-10-16 13:25 ` Linus Walleij
2026-10-15 10:53 ` [PATCH v10 3/8] gpio: pl061: drop redundant pending check in the IRQ handler Long Zhao via B4 Relay
2026-10-15 19:21 ` Andy Shevchenko
2026-10-16 13:29 ` Linus Walleij
2026-10-15 10:53 ` [PATCH v10 4/8] gpio: pl061: convert register access to regmap Long Zhao via B4 Relay
2026-10-15 19:28 ` Andy Shevchenko
2026-10-15 10:53 ` [PATCH v10 5/8] gpio: pl061: use IRQ_TYPE_LEVEL_MASK and IRQ_TYPE_EDGE_BOTH Long Zhao via B4 Relay
2026-10-15 10:53 ` Long Zhao via B4 Relay [this message]
2026-10-15 19:31 ` [PATCH v10 6/8] gpio: pl061: use cleanup helpers for locks Andy Shevchenko
2026-10-15 10:53 ` [PATCH v10 7/8] gpio: pl061: switch data path to gpio-regmap Long Zhao via B4 Relay
2026-10-15 19:48 ` Andy Shevchenko
2026-10-15 10:53 ` [PATCH v10 8/8] gpio: pl061: add Ambarella register-layout variant Long Zhao via B4 Relay
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