From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E80E249A3AC; Fri, 16 Oct 2026 12:33:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1792154031; cv=none; b=A4w9sCFLfRAdKh6GoIi/4nks88J9r32epfNPqwu/rarBnhh1lnrVJma92Hq88T2fkHN1+pY79RN/CFWcXX+0O7WfEDRuoA05D3afjztwi0t0pSfk+yyLSUMBF4hhjfPaJ7G+XzYBavQeXOQKPCwPDo6ue2E/0ts6SmiZ6hMnOWw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1792154031; c=relaxed/simple; bh=JImBorg6tsPSLrGjFVXTci/j4MozISc22iZxnNEBC24=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fd8b89u6r1p7TCI4Kc5+hAQp44eyN5nidCM1GGEeK/rG+4WnmhOLaXP8jmOhm8mdWZLsMe0rqZHa4EpGZ12aXo2CHdk8pZwPSrGWPGbh4Jh5sxFoypep7QJM/j/wdUfYxNzkkU2i/W8+owE0c4fnT5nQXOWiDh0VBGmtL4qcRKA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=nI6FB44k; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="nI6FB44k" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1792154028; bh=JImBorg6tsPSLrGjFVXTci/j4MozISc22iZxnNEBC24=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=nI6FB44kk5RgMNe2RuhsX5105H1xYcTtI2yulY0HpQknq29l9ehfCpzlB+vqLZpg5 U5i/FP79Ud7ivx1fLS0x+8EkN1T05akGhP2gq4NH2PWegbA1dS8lA0GV3x7sp+aGuG Mcoth9v4h6vCqQyRCzB+Glybkw3ylXyRuSTKQC+Tz+e1HW839D9rt8EGWUEfK/n7/8 2+dzreUHiw3tGQ67dMer0QjOGzhN8t315/CWoKhrZsKUUyFdR7ilxDlUhqxRsExJUY 6q3kL6vEF9xX/m4I2VVNzE8aU+CIY90h0eP4u1NDGqTIMOAcE5090C2q/LIGtwvexm 8LvtBILrZYZuQ== Received: from yukiji.home (unknown [100.64.0.131]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: laeyraud) by bali.collaboradmins.com (Postfix) with ESMTPSA id 70FAA17E142F; Fri, 16 Oct 2026 14:33:47 +0200 (CEST) From: Louis-Alexis Eyraud Date: Fri, 16 Oct 2026 14:33:08 +0200 Subject: [PATCH v14 16/23] scsi: ufs: mediatek: Rework _ufs_mtk_clk_scale error paths Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261016-mt8196-ufs-v14-16-e8d565e0cd45@collabora.com> References: <20261016-mt8196-ufs-v14-0-e8d565e0cd45@collabora.com> In-Reply-To: <20261016-mt8196-ufs-v14-0-e8d565e0cd45@collabora.com> To: Chunfeng Yun , Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Peter Wang , Chaotian Jing , Alim Akhtar , Bart Van Assche , Bean Huo , Stanley Jhu , Stanley Jhu , "James E.J. Bottomley" , "Martin K. Petersen" , Philipp Zabel , Liam Girdwood , Mark Brown Cc: kernel@collabora.com, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Nicolas Frattaroli , Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1792154009; l=3592; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=zHoz+yB0mo4JZfKcYe+YYUNZmYWzFUfC70ylza+u7r0=; b=W3MDALg4c0GVZX42vIrGrYZP/sOEaVOQH5sk2SQylrDLtnet+QKQlQ3Sz7fJolb2/6FQa9j/t dTXvev35zGSA167Nw6KcW007wUArzZdFVjSmeivySz4VzYS3JyJukjV X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= From: Nicolas Frattaroli Errors should be printed at the correct log level. Additionally, it looks like some "goto out"'s were omitted in the scale up case, which looks like a mistake, as the scale down branch of the code does use them. Rework the error messages to make them nicer and at the correct verbosity, and add the missing gotos. Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Peter Wang Signed-off-by: Nicolas Frattaroli Signed-off-by: Louis-Alexis Eyraud --- drivers/ufs/host/ufs-mediatek.c | 41 +++++++++++++++++++---------------------- 1 file changed, 19 insertions(+), 22 deletions(-) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c index b8812005b6c4..c370535dc341 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -2043,16 +2043,16 @@ static void _ufs_mtk_clk_scale(struct ufs_hba *hba, bool scale_up) ret = clk_prepare_enable(clki->clk); if (ret) { - dev_info(hba->dev, - "clk_prepare_enable() fail, ret: %d\n", ret); + dev_err(hba->dev, "%s: Failed to enable clock: %pe\n", __func__, ERR_PTR(ret)); return; } if (clk_fde_scale) { ret = clk_prepare_enable(fde_clki->clk); if (ret) { - dev_info(hba->dev, - "fde clk_prepare_enable() fail, ret: %d\n", ret); + dev_err(hba->dev, "%s: Failed to enable FDE clock: %pe\n", + __func__, ERR_PTR(ret)); + clk_disable_unprepare(clki->clk); return; } } @@ -2061,51 +2061,48 @@ static void _ufs_mtk_clk_scale(struct ufs_hba *hba, bool scale_up) if (clk_bind_vcore) { ret = regulator_set_voltage(reg, volt, INT_MAX); if (ret) { - dev_info(hba->dev, - "Failed to set vcore to %d\n", volt); + dev_err(hba->dev, "Failed to set vcore to %d\n", volt); goto out; } } ret = clk_set_parent(clki->clk, mclk->ufs_sel_max_clki->clk); if (ret) { - dev_info(hba->dev, "Failed to set clk mux, ret = %d\n", - ret); + dev_err(hba->dev, "%s: Failed to set clock mux: %pe\n", + __func__, ERR_PTR(ret)); + goto out; } if (clk_fde_scale) { - ret = clk_set_parent(fde_clki->clk, - mclk->ufs_fde_max_clki->clk); + ret = clk_set_parent(fde_clki->clk, mclk->ufs_fde_max_clki->clk); if (ret) { - dev_info(hba->dev, - "Failed to set fde clk mux, ret = %d\n", - ret); + dev_err(hba->dev, "%s: Failed to set fde clock mux: %pe\n", + __func__, ERR_PTR(ret)); + goto out; } } } else { if (clk_fde_scale) { - ret = clk_set_parent(fde_clki->clk, - mclk->ufs_fde_min_clki->clk); + ret = clk_set_parent(fde_clki->clk, mclk->ufs_fde_min_clki->clk); if (ret) { - dev_info(hba->dev, - "Failed to set fde clk mux, ret = %d\n", - ret); + dev_err(hba->dev, "%s: Failed to set fde clock mux: %pe\n", + __func__, ERR_PTR(ret)); goto out; } } ret = clk_set_parent(clki->clk, mclk->ufs_sel_min_clki->clk); if (ret) { - dev_info(hba->dev, "Failed to set clk mux, ret = %d\n", - ret); + dev_err(hba->dev, "%s: Failed to set clock mux: %pe\n", + __func__, ERR_PTR(ret)); goto out; } if (clk_bind_vcore) { ret = regulator_set_voltage(reg, 0, INT_MAX); if (ret) { - dev_info(hba->dev, - "failed to set vcore to MIN\n"); + dev_err(hba->dev, "%s: Failed to set vcore to minimum: %pe\n", + __func__, ERR_PTR(ret)); } } } -- 2.56.0