From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 709D5485516; Fri, 16 Oct 2026 12:33:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1792154035; cv=none; b=f9hE9M/AageoySpNeDW3WWhI6de8pfuTxxrG71CEHjJsXhPCjrV0nos9RPjHUbmB1GAXPcOjUfz7Kv/sVl1Xsvm5vVy5IHrADFKd7hUktgwiTB5X49voWWwUghEikVS55uy5YbcOXuTInOE/mtF2ZTlyNfttZPAnOSj0Iie6M2I= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1792154035; c=relaxed/simple; bh=+wkkIGbmdhWI4lfzyAodJikUYhkW2TLOVz4KnI2vzy8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=G/GtE/YPbwo1f3No21gMmT4ren0R/3u61qj3CrzpgXYIpbjJ9SjIh65huaODtjWhOUfCIWrU1bil0iNDrHMw/GOFd8yyU1I9J9HoHXQgH7+kYh5F0/bdgBsMvrgmf6QJ/GpkdWs0xuBX/JV73EKTvLASXJr9y+k9U53fEn5aWqI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=H7OnW8NK; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="H7OnW8NK" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1792154031; bh=+wkkIGbmdhWI4lfzyAodJikUYhkW2TLOVz4KnI2vzy8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=H7OnW8NK8e6JhORDC0qGFEpT/DzzCRv47NbtWpiRwyFqh3BHVwF5jQb0Z/ZMRKChb 3dMZ7JspCE3PXrmgmK7M80ueORMvY0JoUK7PGuT/vBaw2bVAj3QVtSsNDU88NR8QmI pNJWYIC1zeLxNoxIH8FNEdeVr8uTUXJr1wBNWmK4xh7DsE4J7XVQX0QkBsxyr3dy9y eV3syIfgCuEygV8fUQOUlCe6tcBQYJVTE5rlpC/xLOBGxVDYsC7TUMOhipZO6Y5jg2 QrlBvtjaIhb3ioJv1DaJAhJwWwecVPmZZ6IPL3S39tG0+Zk4SQf/Hk8tPfeiHJ+alU 5aSV2ggJvTKQg== Received: from yukiji.home (unknown [100.64.0.131]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: laeyraud) by bali.collaboradmins.com (Postfix) with ESMTPSA id B940D17E053D; Fri, 16 Oct 2026 14:33:50 +0200 (CEST) From: Louis-Alexis Eyraud Date: Fri, 16 Oct 2026 14:33:11 +0200 Subject: [PATCH v14 19/23] scsi: ufs: mediatek: Don't acquire dvfsrc-vcore twice Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261016-mt8196-ufs-v14-19-e8d565e0cd45@collabora.com> References: <20261016-mt8196-ufs-v14-0-e8d565e0cd45@collabora.com> In-Reply-To: <20261016-mt8196-ufs-v14-0-e8d565e0cd45@collabora.com> To: Chunfeng Yun , Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Peter Wang , Chaotian Jing , Alim Akhtar , Bart Van Assche , Bean Huo , Stanley Jhu , Stanley Jhu , "James E.J. Bottomley" , "Martin K. Petersen" , Philipp Zabel , Liam Girdwood , Mark Brown Cc: kernel@collabora.com, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Nicolas Frattaroli , Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1792154009; l=7871; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=5RjOzi0tRTi+Gz6jrP7hye7vXOZaCXfpNDV+k1zK1qQ=; b=zBJ3IVWUd+BlFXSK8fQgVkcCqqAUjJD15pYiVLj+GngVTYptT1AwbKjDa3XePK6g12F2CMkeP Bg/eualk/KhCeAD9e8xL3AjRigpRfyLQ2Zjx9AeebH14PLp6WGUT2CX X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= From: Nicolas Frattaroli As part of its featureset, the ufs-mediatek driver needs to play with an optional dvfsrc-vcore regulator for some of them. However, it currently does this by acquiring two different references to it in two different places, needlessly duplicating logic. Move reg_vcore to the host struct, acquire it in the same function as avdd09 is acquired, and rework the users of reg_vcore. Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Peter Wang Signed-off-by: Nicolas Frattaroli Signed-off-by: Louis-Alexis Eyraud --- drivers/ufs/host/ufs-mediatek.c | 60 +++++++++++++++++++---------------------- drivers/ufs/host/ufs-mediatek.h | 3 +-- 2 files changed, 28 insertions(+), 35 deletions(-) diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c index 649a8bd96f90..43b19179d024 100644 --- a/drivers/ufs/host/ufs-mediatek.c +++ b/drivers/ufs/host/ufs-mediatek.c @@ -567,7 +567,6 @@ static void ufs_mtk_boost_crypt(struct ufs_hba *hba, bool boost) { struct ufs_mtk_host *host = ufshcd_get_variant(hba); struct ufs_mtk_crypt_cfg *cfg; - struct regulator *reg; int volt, ret; if (!ufs_mtk_is_boost_crypt_enabled(hba)) @@ -575,7 +574,6 @@ static void ufs_mtk_boost_crypt(struct ufs_hba *hba, bool boost) cfg = host->crypt; volt = cfg->vcore_volt; - reg = cfg->reg_vcore; ret = clk_prepare_enable(cfg->clk_crypt_mux); if (ret) { @@ -585,7 +583,7 @@ static void ufs_mtk_boost_crypt(struct ufs_hba *hba, bool boost) } if (boost) { - ret = regulator_set_voltage(reg, volt, INT_MAX); + ret = regulator_set_voltage(host->reg_vcore, volt, INT_MAX); if (ret) { dev_err(hba->dev, "%s: Failed to set vcore to %d: %pe\n", __func__, volt, ERR_PTR(ret)); @@ -596,7 +594,7 @@ static void ufs_mtk_boost_crypt(struct ufs_hba *hba, bool boost) if (ret) { dev_err(hba->dev, "%s: Failed to reparent clk_crypt_perf: %pe\n", __func__, ERR_PTR(ret)); - regulator_set_voltage(reg, 0, INT_MAX); + regulator_set_voltage(host->reg_vcore, 0, INT_MAX); goto out; } } else { @@ -607,7 +605,7 @@ static void ufs_mtk_boost_crypt(struct ufs_hba *hba, bool boost) goto out; } - ret = regulator_set_voltage(reg, 0, INT_MAX); + ret = regulator_set_voltage(host->reg_vcore, 0, INT_MAX); if (ret) { dev_err(hba->dev, "%s: Failed to set vcore to minimum: %pe\n", __func__, ERR_PTR(ret)); @@ -625,15 +623,12 @@ static void ufs_mtk_init_boost_crypt(struct ufs_hba *hba) u32 volt; int ret; - cfg = devm_kzalloc(dev, sizeof(*cfg), GFP_KERNEL); - if (!cfg) + if (!host->reg_vcore) return; - cfg->reg_vcore = devm_regulator_get_optional(dev, "dvfsrc-vcore"); - if (IS_ERR(cfg->reg_vcore)) { - dev_err(dev, "Failed to get dvfsrc-vcore: %pe\n", cfg->reg_vcore); + cfg = devm_kzalloc(dev, sizeof(*cfg), GFP_KERNEL); + if (!cfg) return; - } ret = of_property_read_u32(dev->of_node, "mediatek,boost-crypt-vcore-min", &volt); @@ -939,7 +934,6 @@ static void ufs_mtk_init_clocks(struct ufs_hba *hba) struct list_head *head = &hba->clk_list_head; struct ufs_clk_info *clki, *clki_tmp; struct device *dev = hba->dev; - struct regulator *reg; u32 volt; /* @@ -980,16 +974,8 @@ static void ufs_mtk_init_clocks(struct ufs_hba *hba) return; } - /* - * Default get vcore if dts have these settings. - * No matter clock scaling support or not. (may disable by customer) - */ - reg = devm_regulator_get_optional(dev, "dvfsrc-vcore"); - if (IS_ERR(reg)) { - if (PTR_ERR(reg) != -ENODEV) - dev_err(dev, "Failed to get dvfsrc-vcore: %pe\n", reg); + if (!host->reg_vcore) return; - } if (of_property_read_u32(dev->of_node, "clk-scale-up-vcore-min", &volt)) { @@ -997,12 +983,11 @@ static void ufs_mtk_init_clocks(struct ufs_hba *hba) return; } - host->mclk.reg_vcore = reg; host->mclk.vcore_volt = volt; /* If default boot is max gear, request vcore */ - if (reg && volt && host->clk_scale_up) - if (regulator_set_voltage(reg, volt, INT_MAX)) + if (volt && host->clk_scale_up) + if (regulator_set_voltage(host->reg_vcore, volt, INT_MAX)) dev_err(hba->dev, "Failed to set vcore to %d\n", volt); } @@ -1114,6 +1099,17 @@ static int ufs_mtk_get_supplies(struct ufs_mtk_host *host) const struct ufs_mtk_soc_data *data = of_device_get_match_data(dev); int ret; + host->reg_vcore = devm_regulator_get_optional(dev, "dvfsrc-vcore"); + if (IS_ERR(host->reg_vcore)) { + if (PTR_ERR(host->reg_vcore) != -ENODEV) { + return dev_err_probe(dev, + PTR_ERR(host->reg_vcore), + "Failed to get dvfsrc-vcore supply: %pe\n", + host->reg_vcore); + } + host->reg_vcore = NULL; + } + if (!data) return 0; @@ -1182,6 +1178,10 @@ static int ufs_mtk_init(struct ufs_hba *hba) host->hba = hba; ufshcd_set_variant(hba, host); + err = ufs_mtk_get_supplies(host); + if (err) + goto out_variant_clear; + /* Initialize host capability */ ufs_mtk_init_host_caps(hba); @@ -1236,10 +1236,6 @@ static int ufs_mtk_init(struct ufs_hba *hba) ufs_mtk_init_clocks(hba); - err = ufs_mtk_get_supplies(host); - if (err) - goto out_phy_exit; - /* * ufshcd_vops_init() is invoked after * ufshcd_setup_clock(true) in ufshcd_hba_init() thus @@ -2001,7 +1997,6 @@ static void _ufs_mtk_clk_scale(struct ufs_hba *hba, bool scale_up) struct ufs_mtk_clk *mclk = &host->mclk; struct ufs_clk_info *clki = mclk->ufs_sel_clki; struct ufs_clk_info *fde_clki = mclk->ufs_fde_clki; - struct regulator *reg; int volt, ret = 0; bool clk_bind_vcore = false; bool clk_fde_scale = false; @@ -2012,9 +2007,8 @@ static void _ufs_mtk_clk_scale(struct ufs_hba *hba, bool scale_up) if (!clki || !fde_clki) return; - reg = host->mclk.reg_vcore; volt = host->mclk.vcore_volt; - if (reg && volt != 0) + if (host->reg_vcore && volt) clk_bind_vcore = true; if (mclk->ufs_fde_max_clki && mclk->ufs_fde_min_clki) @@ -2038,7 +2032,7 @@ static void _ufs_mtk_clk_scale(struct ufs_hba *hba, bool scale_up) if (scale_up) { if (clk_bind_vcore) { - ret = regulator_set_voltage(reg, volt, INT_MAX); + ret = regulator_set_voltage(host->reg_vcore, volt, INT_MAX); if (ret) { dev_err(hba->dev, "Failed to set vcore to %d\n", volt); goto out; @@ -2078,7 +2072,7 @@ static void _ufs_mtk_clk_scale(struct ufs_hba *hba, bool scale_up) } if (clk_bind_vcore) { - ret = regulator_set_voltage(reg, 0, INT_MAX); + ret = regulator_set_voltage(host->reg_vcore, 0, INT_MAX); if (ret) { dev_err(hba->dev, "%s: Failed to set vcore to minimum: %pe\n", __func__, ERR_PTR(ret)); diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediatek.h index d97951ee1f4e..6b81c8f76201 100644 --- a/drivers/ufs/host/ufs-mediatek.h +++ b/drivers/ufs/host/ufs-mediatek.h @@ -141,7 +141,6 @@ enum ufs_mtk_host_caps { }; struct ufs_mtk_crypt_cfg { - struct regulator *reg_vcore; struct clk *clk_crypt_perf; struct clk *clk_crypt_mux; struct clk *clk_crypt_lp; @@ -155,7 +154,6 @@ struct ufs_mtk_clk { struct ufs_clk_info *ufs_fde_clki; /* Mux */ struct ufs_clk_info *ufs_fde_max_clki; /* Max src */ struct ufs_clk_info *ufs_fde_min_clki; /* Min src */ - struct regulator *reg_vcore; int vcore_volt; }; @@ -175,6 +173,7 @@ struct ufs_mtk_host { struct phy *mphy; struct regulator *reg_avdd09; struct regulator *reg_avdd09_1; + struct regulator *reg_vcore; struct reset_control_bulk_data resets[MTK_UFS_NUM_RESETS]; struct ufs_hba *hba; struct ufs_mtk_crypt_cfg *crypt; -- 2.56.0