[PATCH v2 00/23] coresight: trbe: Refactor buffer and IRQ handling

[Leo Yan <leo.yan@arm.com>]

This series follows the earlier TRBE buffer refactoring posting [1].
The work is now split into two parts. This first part contains fixes
and refactoring in preparation for wrap and trigger mode support.
Support for those modes will be sent separately.

The patches are grouped as follows for easier review:

  Patches 1-5: Minor fixes
    Add register definitions, fix the watermark range check, and
    improve erratum checks and perf handle validation.

  Patches 6-11: Enable/disable lifecycle fixes
    Clean up session setup, status clearing and IRQ handle ownership.

  Patches 12-17: Refine status classification
    Decode stop reasons, report truncation on errors and improve
    trace-size accounting.

  Patches 18-23: Improve IRQ and overflow handling
    Keep the handle in per-CPU data, stabilize status reads, and
    improve AUX restarts and trace-gap reporting.

A race also remains between TRBE interrupt handling and AUX pause/resume
from a sampling NMI. This should be resolved as part of the state
machine refactoring in the CoreSight AUX sampling series [2].

[1] https://lore.kernel.org/linux-arm-kernel/20251201-trbe_buffer_refactor_v1-1-v1-0-7da32b076b28@arm.com/
[2] https://lore.kernel.org/linux-arm-kernel/20260915-arm_cs_support_aux_sample-v1-0-35cf6f297d20@arm.com/T/#t

Signed-off-by: Leo Yan <leo.yan@arm.com>
---
Leo Yan (23):
      arm64/sysreg: Define TRBSR_EL1.EC event classes
      coresight: trbe: Make watermark range check overflow safe in __trbe_normal_offset()
      coresight: trbe: Use helpers for checking errata
      coresight: trbe: Check the buffer association before IRQ validation
      coresight: trbe: Validate perf handle before using sink data
      coresight: trbe: Drop redundant disable from enable path
      coresight: trbe: Publish the session after successful enable
      coresight: trbe: Clear stale external abort status
      coresight: trbe: Clear TRBSR status at stop sites
      coresight: trbe: Drop redundant disables
      coresight: trbe: Assign the perf handle in enable and disable
      coresight: trbe: Decode TRBSR status codes
      coresight: trbe: Simplify wrap status handling
      coresight: trbe: Treat access not allowed stops as fatal
      coresight: trbe: Report truncated trace on buffer update errors
      coresight: trbe: Always classify TRBSR when updating buffer
      coresight: trbe: Calculate trace size across buffer wrap
      coresight: trbe: Keep the perf handle in per-CPU data
      coresight: trbe: Reload the AUX buffer on overflow restart
      coresight: trbe: Add fault action argument to trbe_handle_overflow()
      coresight: trbe: Read TRBSR after prohibiting and flushing trace
      coresight: trbe: Restart trace source for stopped buffers
      coresight: trbe: Report trace gaps with PARTIAL instead of COLLISION

 arch/arm64/include/asm/sysreg.h              |   6 +
 arch/arm64/tools/sysreg                      |   8 +-
 drivers/hwtracing/coresight/coresight-trbe.c | 481 ++++++++++++++++++---------
 drivers/hwtracing/coresight/coresight-trbe.h |   8 -
 4 files changed, 345 insertions(+), 158 deletions(-)
---
base-commit: 343cfcbb3ecfdb80aa576a428cfa3b65ad783842
change-id: 20261016-trbe_enable_disable_irq_handle_refactor-0a3450f03473

Best regards,
-- 
Leo Yan <leo.yan@arm.com>