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Received: from localhost.localdomain(mailfrom:fangyu.yu@linux.alibaba.com fp:SMTPD_---0XCtC-XB_1792119699 cluster:ay36) by smtp.aliyun-inc.com; Fri, 16 Oct 2026 11:01:41 +0800 From: fangyu.yu@linux.alibaba.com To: jgg@nvidia.com Cc: alex@ghiti.fr, andrew.jones@oss.qualcomm.com, aou@eecs.berkeley.edu, fangyu.yu@linux.alibaba.com, gsh517025@gmail.com, guoren@kernel.org, iommu@lists.linux.dev, jgg@ziepe.ca, joro@8bytes.org, jroedel@suse.de, kvm-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, palmer@dabbelt.com, pjw@kernel.org, robin.murphy@arm.com, tomasz.jeznach@linux.dev, will@kernel.org, zong.li@sifive.com Subject: Re: [RFC PATCH v2 3/4] iommu/riscv: Add guest IMSIC GPA mapping helpers Date: Fri, 16 Oct 2026 11:01:38 +0800 Message-Id: <20261016030138.91675-1-fangyu.yu@linux.alibaba.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <179210803193.58760.10996339526486124321.b4-reply@b4> References: <179210803193.58760.10996339526486124321.b4-reply@b4> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit >> From: Fangyu Yu >> >> IOMMU implementations without the MSI_FLAT capability translate MSI >> writes through the second-stage page table, so IRQ forwarding on them >> will need guest IMSIC pages mapped into the second-stage domain. >> >> Add an xarray to the MSI table that tracks the HPA installed for each >> mapped guest IMSIC GPA, and two helpers for use with the MSI table lock >> held: riscv_iommu_msi_table_map_gpa() installs the initial 4 KiB >> mapping, and riscv_iommu_msi_table_replace_gpa() repoints the leaf PTE >> when a vCPU's VS-file host page moves, using the generic page table >> replace_leaf op instead of walking the table in the driver. >> >> Signed-off-by: Fangyu Yu >> --- >> drivers/iommu/riscv/iommu.c | 43 +++++++++++++++++++++++++++++++++++++ >> drivers/iommu/riscv/iommu.h | 12 +++++++++++ >> 2 files changed, 55 insertions(+) >> >> diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c >> index e2e77469ea3c..88e131ce96c1 100644 >> --- a/drivers/iommu/riscv/iommu.c >> +++ b/drivers/iommu/riscv/iommu.c >> @@ -1217,6 +1217,42 @@ void riscv_iommu_msi_table_inval_all(struct riscv_iommu_msi_table *msi_table) >> riscv_iommu_iotlb_inval(domain, &gather); >> } >> >> +int riscv_iommu_msi_table_map_gpa(struct riscv_iommu_msi_table *msi_table, >> + dma_addr_t gpa, phys_addr_t hpa) >> +{ >> + struct riscv_iommu_domain *domain = >> + container_of(msi_table, struct riscv_iommu_domain, msi_table); >> + const int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO; >> + >> + /* Guest IMSIC GPA mapping only exists in second-stage translations. */ >> + if (!domain->gscid) >> + return -EOPNOTSUPP; >> + >> + return iommu_map(&domain->domain, gpa, hpa, IMSIC_MMIO_PAGE_SZ, prot, >> + GFP_ATOMIC); >> +} > >Andrew has moved well past a v3 > >I shouldn't be seeing code in iommu or irq drivers directly mapping into >domains. That doesn't work, Andrew's latest series don't do this. > >It still needs to use the SW_MSI mechanism and related. > Andrew has posted two patch series in the community: one is the MSI remap v6 series[1], and another is the IRQ bypass v3 series[2]. I think you are referring to the MSI remap v6 series. My patch was based on the IRQ bypass v3 series, and I added this patch on top of it. [1] https://lore.kernel.org/linux-iommu/179209292714.4133959.5997128071302263244.b4-review@b4/T/#t [2] https://lore.kernel.org/linux-riscv/20260928143113.49838-1-andrew.jones@oss.qualcomm.com/ >Nothing in the commit messages clearly explained what this is actually for >without having to go dig up the riscv manuals again. Please explain how the >interrupt translation works and what actual user visible problem this is >trying to solve is. > The interrupt translation is based on Andrew's irq bypass patch description. RISC-V IOMMU defines an optional MSI page table feature, which can be used to implement irq bypass by translating the vIMSIC GPA to the pIMSIC HPA. My patch complements that design. If the RISC-V IOMMU hardware does not implement the MSI page table, then the second-stage page table can be used instead to map vIMSIC GPA to pIMSIC HPA. Thanks, Fangyu >-- >Jason