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Fri, 16 Oct 2026 00:40:41 -0700 From: Manikanta Maddireddy To: , , , , , CC: , , , , , , , Subject: [PATCH v2 0/5] PCI: dwc: Clean up RAS-DES and register field handling Date: Fri, 16 Oct 2026 13:10:21 +0530 Message-ID: <20261016074026.564302-1-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: EA8PEPF00000008:EE_|CY8PR12MB7657:EE_ X-MS-Office365-Filtering-Correlation-Id: d5a88254-d039-4c1b-ae24-08df2b58d5c3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|7416014|376014|1800799024|82310400026|36860700016|11063799006|56012099006|261009223027099003|18002099003|10067099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 4l+HlPP6qKex3AQP4M0z9oQ7B6fH+/U9HT7u5fi65oPdeZWMxrog1PCorNHChVRT3+32BhfS7VrrqFcuaXb+7gtU24NQeSwrpEdqDHi5r9zj2mnZkTnfd9M37kEXJSabxi55Zy3uhuP+ivzGskrF2KS9OmTpRKZ60jUgWmkci92M7eLIJm6G3YkttURuHjBjFGTFucXSD9Kvbea9+ndrvUOSNFirUm0GBUqib6x8sTgdhe/KqrodxAI5J8yIUi4j9HMXVMYLBAXK43GfgFbR7WzdGUhW1s/nX94w36dsGlO2khyPCsL8PzFikt4n4I1i8nrO+O3c/ACLJDbI8pwIHnKMMr/i/9VrGynqrVo1/Znsl5vdCkL5TuZDw05IMNU2H4T4CUROwiWrQRQ5yIKDQ88SomodDnCKw5Eh/IFEKlzFuQo2MRcfRPmumG+sVEHd X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Oct 2026 07:41:05.2292 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d5a88254-d039-4c1b-ae24-08df2b58d5c3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: EA8PEPF00000008.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7657 This series addresses review feedback around register field handling in the DWC PCIe code and the Tegra194 PCIe driver. The first patches add shared masks for the RAS-DES event counter fields, convert Tegra194 register programming to FIELD_PREP()/FIELD_MODIFY(), and drop shift macros that become unused after the conversion. The final patches make Tegra194 use the common RAS-DES selector definitions and consolidate the event counter field definitions in the DWC header. There should be no functional change intended beyond making the bitfield programming explicit and keeping the shared RAS-DES definitions in one place. Manikanta Maddireddy (5): PCI: dwc: Add RAS event counter field masks PCI: tegra194: Use FIELD_*() for register fields PCI: dwc: Drop unused shift macros PCI: tegra194: Use standard RAS event selector mask PCI: dwc: Consolidate RAS-DES event counter fields .../controller/dwc/pcie-designware-debugfs.c | 56 ++++--- drivers/pci/controller/dwc/pcie-designware.h | 10 +- drivers/pci/controller/dwc/pcie-tegra194.c | 145 +++++++++--------- 3 files changed, 106 insertions(+), 105 deletions(-) -- 2.34.1