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Fri, 16 Oct 2026 00:40:55 -0700 From: Manikanta Maddireddy To: , , , , , CC: , , , , , , , Subject: [PATCH v2 3/5] PCI: dwc: Drop unused shift macros Date: Fri, 16 Oct 2026 13:10:24 +0530 Message-ID: <20261016074026.564302-4-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20261016074026.564302-1-mmaddireddy@nvidia.com> References: <20261016074026.564302-1-mmaddireddy@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: EA8PEPF0000000C:EE_|MN2PR12MB4375:EE_ X-MS-Office365-Filtering-Correlation-Id: 4ff94bc3-1a3b-4090-8cba-08df2b58de0c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|1800799024|23010399003|82310400026|36860700016|56012099006|5023799004|11063799006|261009223027099003|10067099003|18002099003|22082099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Pof9U+bi/nYSQxLuT4TQpekqRIeoqQ7lDK+vzQIlp2pZdiY97dxmpgg/VvssoMTL4ZBJAbYvKWYNp4YtsWKTbxCQ5X6NQHNnhbMVsMKxvIRm4PHg0qdT3U1bLMxStpu2WAdiLkHNNgnyztz6Jq767EtIPvRBzgCTzWTho0WDb4BTmxyrqTwrxZYqUmNzzCDkcWmqaCIIlP5lUGG53EjiMSG3WGE94B6B0OyIYT6po/srEU1Y7o8wmvu3dyz3czeE8ZRRe473pVUh12Q5H2Yf1qsyb669qBa8azs4afR5UPxzp2lox7YZPGi9WyJYGMNGtonmaJH5zi6sbY7CJI2wGsgFSJBnjH7lRNuPNQUcub3HOgHeq0ErxFpTOgBj5/0D8uTIisQ/HHIDMr/iFpYYd2ItrgO1UnMr2FN1bmNNHVvQHIVkfcDl+kAY7zZcP7AN X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Oct 2026 07:41:19.1467 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4ff94bc3-1a3b-4090-8cba-08df2b58de0c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: EA8PEPF0000000C.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4375 Tegra no longer uses the DesignWare field shift macros after converting the call sites to FIELD_PREP() and FIELD_MODIFY(). Remove the unused shift macros and the old narrow event-selector mask. Add the complete event-selector field with the standard mask name, and keep a temporary alias so existing users keep building until they are converted. Signed-off-by: Manikanta Maddireddy --- drivers/pci/controller/dwc/pcie-designware.h | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index fa51c81f315c..cb1d1a98e61a 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -85,9 +85,7 @@ /* Common Clock N_FTS */ #define PORT_AFAC_CC_N_FTS(n) FIELD_PREP(PORT_AFAC_CC_N_FTS_MASK, n) #define PORT_AFAC_ENTER_ASPM BIT(30) /* ASPM L1 Entry Control */ -#define PORT_AFAC_L0S_ELS 24 /* L0s Entrance Latency shift */ #define PORT_AFAC_L0S_ELM GENMASK(26, 24) /* L0s Entrance Latency mask */ -#define PORT_AFAC_L1_ELS 27 /* L1 Entrance Latency shift */ #define PORT_AFAC_L1_ELM GENMASK(29, 27) /* L1 Entrance Latency mask */ #define PORT_LINK_CTRL 0x710 /* Port Link Control Register */ @@ -161,7 +159,6 @@ #define GEN3_CTRL_EQ_PHASE_2_3 BIT(9) /* Equalization Phase 2 and Phase 3 */ #define GEN3_CTRL_RXEQ_RGRDLESS_RXTS BIT(13) #define GEN3_CTRL_GEN3_EQ_DISABLE BIT(16) /* Equalization Disable */ -#define GEN3_CTRL_RATE_SHADOW_SEL_SHIFT 24 /* Rate Shadow Select shift */ #define GEN3_CTRL_RATE_SHADOW_SEL_MASK GENMASK(25, 24) /* Rate Shadow Select mask */ #define GEN3_EQ_CTRL 0x8A8 /* Gen3 EQ Control */ @@ -279,17 +276,14 @@ #define RAS_DES_EVENT_COUNTER_CONTROL 0x8 #define EVENT_COUNTER_ALL_CLEAR 0x3 #define EVENT_COUNTER_ENABLE_ALL 0x7 -#define EVENT_COUNTER_ENABLE_SHIFT 2 #define EVENT_COUNTER_ENABLE_MASK GENMASK(4, 2) -#define EVENT_COUNTER_EVENT_SEL_MASK GENMASK(7, 0) -#define EVENT_COUNTER_EVENT_SEL_SHIFT 16 -#define EVENT_COUNTER_EVENT_SEL_FIELD_MASK GENMASK(23, 16) +#define EVENT_COUNTER_EVENT_SEL_MASK GENMASK(23, 16) +#define EVENT_COUNTER_EVENT_SEL_FIELD_MASK EVENT_COUNTER_EVENT_SEL_MASK #define EVENT_COUNTER_EVENT_Tx_L0S 0x2 #define EVENT_COUNTER_EVENT_Rx_L0S 0x3 #define EVENT_COUNTER_EVENT_L1 0x5 #define EVENT_COUNTER_EVENT_L1_1 0x7 #define EVENT_COUNTER_EVENT_L1_2 0x8 -#define EVENT_COUNTER_GROUP_SEL_SHIFT 24 #define EVENT_COUNTER_GROUP_SEL_MASK GENMASK(27, 24) #define EVENT_COUNTER_GROUP_5 0x5 -- 2.34.1