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[159.2.239.150]) by smtp.gmail.com with ESMTPSA id af79cd13be357-93f1a19ce5asm271055585a.32.2026.10.16.11.03.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Oct 2026 11:03:04 -0700 (PDT) Received: from jgg by wakko with local (Exim 4.97) (envelope-from ) id 1xHmGk-00000002F39-2Fc1; Fri, 16 Oct 2026 15:03:02 -0300 Date: Fri, 16 Oct 2026 15:03:02 -0300 From: Jason Gunthorpe To: Daniel Mentz Cc: Robin Murphy , iommu@lists.linux.dev, will@kernel.org, joro@8bytes.org, nicolinc@nvidia.com, smostafa@google.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, dawei.li@linux.dev, praan@google.com Subject: Re: [PATCH v2] iommu/arm-smmu-v3: Align memory attributes for SMMU-originated accesses Message-ID: <20261016180302.GI14213@ziepe.ca> References: <20261004195027.227748-1-danielmentz@google.com> <92758f79-d5b7-4c15-a55d-6bea5f84a028@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Mon, Oct 05, 2026 at 02:26:08PM -0700, Daniel Mentz wrote: > On Mon, Oct 5, 2026 at 9:42 AM Robin Murphy wrote: > > This still isn't answering the question of "why?" though. Yes the > > architecture says some things, but if we were strict about avoiding > > mismatched attributes then Linux couldn't ever support non-coherent DMA > > at all! Similarly while the architecture does permit SMMU > > implementations to be picky about their output attributes, does any such > > implementation actually exist at all, let alone in a system capable of > > running mainline Linux? > > Fair point that existing implementations have been forgiving in > practice. My thinking here is simply that a small, self-contained > cleanup that brings the driver into line with the architecture spec is > worthwhile on its own merits, even without a known implementation where > this currently causes problems. I think we should fix this. At least we have HW that respects these attributes and they have a performance impact depending on how they are set. Fortunately at least our HW does not have a functional "mismatched attribute" issue. If the FW has selected to run the SMMU in non-coherent mode then all of the bits should be set to ask the SMMU to run non-coherent. Ditto for coherent. No sense in giving up performance due to mis set bits. These IP integrations are complicated, the FW may be saying to use non-coherent because some small slice of the system needs that. It doesn't mean that every access on every bus the SMMU has is forced non-coherent. Jason