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[159.2.239.150]) by smtp.gmail.com with ESMTPSA id af79cd13be357-93f23eb7ba5sm131256785a.27.2026.10.16.11.05.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Oct 2026 11:05:22 -0700 (PDT) Received: from jgg by wakko with local (Exim 4.97) (envelope-from ) id 1xHmIz-00000002FIM-2VOf; Fri, 16 Oct 2026 15:05:21 -0300 Date: Fri, 16 Oct 2026 15:05:21 -0300 From: Jason Gunthorpe To: Daniel Mentz Cc: iommu@lists.linux.dev, will@kernel.org, robin.murphy@arm.com, joro@8bytes.org, nicolinc@nvidia.com, smostafa@google.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, dawei.li@linux.dev, praan@google.com Subject: Re: [PATCH v2] iommu/arm-smmu-v3: Align memory attributes for SMMU-originated accesses Message-ID: <20261016180521.GJ14213@ziepe.ca> References: <20261004195027.227748-1-danielmentz@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20261004195027.227748-1-danielmentz@google.com> On Sun, Oct 04, 2026 at 07:50:27PM +0000, Daniel Mentz wrote: > The SMMU specification defines several types of SMMU-originated memory > accesses, including Stage 1 and Stage 2 translation table walks, stream > table accesses (L1STD and STE fetches), CD table accesses (L1CD and CD > fetches), and queue accesses (CMDQ fetch, EVENTQ write, PRIQ write). > > While the memory attributes used for Stage 1 and Stage 2 translation > table walks are configured in io-pgtable-arm based on whether the SMMU > is coherent (ARM_SMMU_FEAT_COHERENCY), the attributes for stream tables, > CD tables, and queues are currently hardcoded to Inner Shareable, > Write-Back. > > On non-coherent systems, however, memory for stream tables, CD tables, > and queues is allocated via dma_alloc_coherent() / > dmam_alloc_coherent(), which provides CPU mappings with Normal > Non-Cacheable attributes. Having a non-coherent SMMU access these > buffers with Inner Shareable, Write-Back attributes results in > mismatched memory attributes between the CPU and the SMMU. > > Configure the memory attributes for tables and queues in > arm_smmu_device_reset() and arm_smmu_make_cdtable_ste() based on > ARM_SMMU_FEAT_COHERENCY, matching the attributes used for translation > table walks: > > - In SMMU_CR1, use Outer Shareable, Non-Cacheable for non-coherent > SMMUs, while retaining Inner Shareable, Write-Back for coherent SMMUs. > This applies to stream table accesses as well as queue accesses (CMDQ > fetch, EVENTQ write, PRIQ write). > - In STE.{S1CIR, S1COR, S1CSH}, use Outer Shareable, Non-Cacheable for > non-coherent SMMUs, while retaining Inner Shareable, Write-Back > Read-Allocate for coherent SMMUs. This applies to CD table accesses. > > Assisted-by: LLM > Reviewed-by: Nicolin Chen > Signed-off-by: Daniel Mentz > --- > Changes in v2: > - Rename local variables 'cache' and 'sh' to 'cr1_cache' and 'cr1_sh' in > arm_smmu_device_reset() (Nicolin, Will) > - Collect Reviewed-by from Nicolin > - Link to v1: https://lore.kernel.org/linux-iommu/20260929032229.3532247-1-danielmentz@google.com/ > > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 37 +++++++++++++++------ > 1 file changed, 27 insertions(+), 10 deletions(-) I think this looks OK Reviewed-by: Jason Gunthorpe Did you check the spec that this is every access? I remember there is a table outlining every access and where the memory attribute lives? Jason