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[70.187.214.22]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1831a6f58c2sm11570790c88.11.2026.10.16.11.16.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Oct 2026 11:16:42 -0700 (PDT) From: Florian Fainelli To: linux-mips@vger.kernel.org Cc: manuel.lauss@gmail.com, Florian Fainelli , Thomas Bogendoerfer , Thierry Reding , "Rafael J. Wysocki (Intel)" , Thomas Gleixner , Dmitry Ilvokhin , linux-kernel@vger.kernel.org (open list) Subject: [PATCH] MIPS: Alchemy: Register interrupt chips with the IRQ core Date: Fri, 16 Oct 2026 11:15:59 -0700 Message-ID: <20261016181602.2152632-1-f.fainelli@gmail.com> X-Mailer: git-send-email 2.53.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Alchemy initializes its interrupt chips through the set-type callbacks, which use irq_set_chip_handler_name_locked() to assign the chip and flow handler. This bypasses irq_set_chip() and its descriptor registration. Since /proc/interrupts switched to iterating the IRQ descriptor maple tree, the statically allocated Alchemy descriptors are no longer found. On an MTX-1, the file contains only the CPU header and ERR counter even though the timer, serial, Ethernet and PCI wireless interrupts work. Register each IC0/IC1 interrupt chip through irq_set_chip() before setting the initial trigger type. Do the same for the Au1300 GPIC. Keep the locked set-type callbacks for later trigger changes. Fixes: 171cc0d9eed1 ("genirq/proc: Speed up /proc/interrupts iteration") Signed-off-by: Florian Fainelli --- arch/mips/alchemy/common/irq.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/mips/alchemy/common/irq.c b/arch/mips/alchemy/common/irq.c index 2403afcd2fb9..d2fa8731fb3c 100644 --- a/arch/mips/alchemy/common/irq.c +++ b/arch/mips/alchemy/common/irq.c @@ -892,15 +892,21 @@ static void __init au1000_init_irq(struct alchemy_irqmap *map) mips_cpu_irq_init(); /* register all 64 possible IC0+IC1 irq sources as type "none". + * Register each chip with the IRQ core before setting its type so + * the descriptors are included in interrupt enumeration. * Use set_irq_type() to set edge/level behaviour at runtime. */ for (irq_nr = AU1000_INTC0_INT_BASE; - (irq_nr < AU1000_INTC0_INT_BASE + 32); irq_nr++) + (irq_nr < AU1000_INTC0_INT_BASE + 32); irq_nr++) { + irq_set_chip(irq_nr, &au1x_ic0_chip); au1x_ic_settype(irq_get_irq_data(irq_nr), IRQ_TYPE_NONE); + } for (irq_nr = AU1000_INTC1_INT_BASE; - (irq_nr < AU1000_INTC1_INT_BASE + 32); irq_nr++) + (irq_nr < AU1000_INTC1_INT_BASE + 32); irq_nr++) { + irq_set_chip(irq_nr, &au1x_ic1_chip); au1x_ic_settype(irq_get_irq_data(irq_nr), IRQ_TYPE_NONE); + } /* * Initialize IC0, which is fixed per processor. @@ -947,6 +953,7 @@ static void __init alchemy_gpic_init_irq(const struct alchemy_irqmap *dints) /* register an irq_chip for them, with 2nd highest priority */ for (i = ALCHEMY_GPIC_INT_BASE; i <= ALCHEMY_GPIC_INT_LAST; i++) { + irq_set_chip(i, &au1300_gpic); au1300_set_irq_priority(i, 1); au1300_gpic_settype(irq_get_irq_data(i), IRQ_TYPE_NONE); } -- 2.53.0