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[2a02:3100:a951:9501:1471:d90c:a21f:9dd7]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48dfd540bc4sm7177387f8f.2.2026.10.16.13.31.02 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 16 Oct 2026 13:31:03 -0700 (PDT) From: Karl Mehltretter To: Paul Walmsley , Palmer Dabbelt Cc: Karl Mehltretter , Albert Ou , Alexandre Ghiti , Aleksa Paunovic , Djordje Todorovic , Michael Neuling , Raj Vishwanathan4 , Aleksandar Rikalo , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [RFT PATCH] riscv: errata: mips: Skip vendor extension lookup during early alternatives Date: Fri, 16 Oct 2026 22:30:52 +0200 Message-Id: <20261016203052.2026-1-kmehltretter@gmail.com> X-Mailer: git-send-email 2.39.5 (Apple Git-154) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit When an enabled erratum selects RISCV_ALTERNATIVE_EARLY, apply_early_boot_alternatives() calls the MIPS errata callback from setup_vm() with the MMU disabled. Each enabled P8700 probe calls riscv_isa_vendor_extension_available() before rejecting RISCV_ALTERNATIVES_EARLY_BOOT, although neither workaround is applied in that stage. KASAN instrumentation in __riscv_isa_vendor_extension_available() reads shadow memory with satp=0. On QEMU's mips-p8700 model this raises a load access fault, and the temporary trap vector parks the boot hart. The guest prints nothing after the OpenSBI handoff. Move the existing early-stage rejection before the extension lookup in both probes. All later stages retain their existing lookup and patch selection. Fixes: 0b0ca959d206 ("riscv: errata: Fix the PAUSE Opcode for MIPS P8700") Fixes: 2cf0b2992203 ("riscv: Add ERRATA_MIPS_P8700_WFI to replace WFI with mips.pause") Assisted-by: LLM Signed-off-by: Karl Mehltretter --- Based on RISC-V for-next commit a5ae1bf65cee. Tested with QEMU 11.0.2, virt/mips-p8700, four harts, and generic KASAN: - The parent reached the OpenSBI handoff but produced no Linux output in 120 seconds. - The patched kernel initialized KASAN, brought all four harts online, and powered off cleanly. - With a DTB advertising xmipsexectl, all 414 PAUSE and 6 WFI sites in live kernel text contained mips.pause. QEMU does not model the physical WFI translation erratum or P8700 PAUSE behavior. This was not tested on P8700 hardware. Please test with KASAN and both P8700 errata enabled. arch/riscv/errata/mips/errata.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/riscv/errata/mips/errata.c b/arch/riscv/errata/mips/errata.c index 6e71555274501..9bb1c3de9504e 100644 --- a/arch/riscv/errata/mips/errata.c +++ b/arch/riscv/errata/mips/errata.c @@ -18,10 +18,10 @@ static inline bool errata_probe_pause(unsigned int stage) if (!IS_ENABLED(CONFIG_ERRATA_MIPS_P8700_PAUSE_OPCODE)) return false; - if (!riscv_isa_vendor_extension_available(MIPS_VENDOR_ID, XMIPSEXECTL)) + if (stage == RISCV_ALTERNATIVES_EARLY_BOOT) return false; - if (stage == RISCV_ALTERNATIVES_EARLY_BOOT) + if (!riscv_isa_vendor_extension_available(MIPS_VENDOR_ID, XMIPSEXECTL)) return false; return true; @@ -32,10 +32,10 @@ static inline bool errata_probe_wfi(unsigned int stage) if (!IS_ENABLED(CONFIG_ERRATA_MIPS_P8700_WFI)) return false; - if (!riscv_isa_vendor_extension_available(MIPS_VENDOR_ID, XMIPSEXECTL)) + if (stage == RISCV_ALTERNATIVES_EARLY_BOOT) return false; - if (stage == RISCV_ALTERNATIVES_EARLY_BOOT) + if (!riscv_isa_vendor_extension_available(MIPS_VENDOR_ID, XMIPSEXECTL)) return false; return true; base-commit: a5ae1bf65cee84bcc121d659e7e22a767853f5f5 -- 2.39.5 (Apple Git-154)