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Fri, 16 Oct 2026 22:10:24 +0000 Date: Fri, 16 Oct 2026 15:10:21 -0700 From: Matt Roper To: Helen Koike CC: , , , , , , Subject: Re: [PATCH v3] drm/xe/lrc: Restore CTX_CS_INDIRECT_CTX_OFFSET programming for pre-Xe2 Message-ID: <20261016221021.GC1329272@mdroper-desk1> References: <20261016214112.1647202-1-koike@igalia.com> Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20261016214112.1647202-1-koike@igalia.com> X-ClientProxiedBy: SJ0PR13CA0059.namprd13.prod.outlook.com (2603:10b6:a03:2c2::34) To DS0PR11MB8182.namprd11.prod.outlook.com (2603:10b6:8:163::17) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS0PR11MB8182:EE_|LV2PR11MB931619:EE_ X-MS-Office365-Filtering-Correlation-Id: 776b6394-54c7-4a8d-68cf-08df2bd246c7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|366016|376014|23010399003|56012099006|261009223027099003|261009221227099003|11063799006|18002099003|22082099003|10067099003; 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Thus, at restore, 0x0 is programmed back to the GPU, which is > an invalid value according to the PRM. > > This causes sporadic hangs on Alder Lake when executing test > IntelAngleEnd2EndTestCases (error VK_DEVICE_LOST). > > Fix it by partially reverting commit c9dfd66cb91e ("drm/xe/lrc: Allow > INDIRECT_CTX for more engine classes"). Re-add the programming of > CTX_CS_INDIRECT_CTX_OFFSET for pre-Xe2 (in theory it should apply to all > platforms, but we got an unexpected behaviour on Xe2 that still requires > investigation). > > Fixes: c9dfd66cb91e ("drm/xe/lrc: Allow INDIRECT_CTX for more engine classes") > Suggested-by: Tvrtko Ursulin > Signed-off-by: Helen Koike Reviewed-by: Matt Roper > > --- > > v3: > - Commit message update: > - s/programed/programmed > - s/for ADL/for pre-Xe2 > - Add sentence saying it should apply to Xe2 too, but we got an > unexpected behaviour and it requires more investigation. > - Remove comment "Enable INDIRECT_CTX leaving..." since it is wrong. > > v2: > - according to intel CI results, it seems that this default is not valid for > LNL and BMG platforms, so limit the change only to ADL. > - program the default only on ADL. > - restore the comment, but add note with exception for ADL. > - update the commit title/message with "for ADL". > --- > drivers/gpu/drm/xe/regs/xe_lrc_layout.h | 3 +++ > drivers/gpu/drm/xe/xe_lrc.c | 8 ++++---- > 2 files changed, 7 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/xe/regs/xe_lrc_layout.h b/drivers/gpu/drm/xe/regs/xe_lrc_layout.h > index 4ab86fc369fd..e4c7c3549735 100644 > --- a/drivers/gpu/drm/xe/regs/xe_lrc_layout.h > +++ b/drivers/gpu/drm/xe/regs/xe_lrc_layout.h > @@ -43,4 +43,7 @@ > #define INDIRECT_CTX_RING_START_UDW (0x08 + 1) > #define INDIRECT_CTX_RING_CTL (0x0a + 1) > > +#define CTX_INDIRECT_CTX_OFFSET_MASK REG_GENMASK(15, 6) > +#define CTX_INDIRECT_CTX_OFFSET_DEFAULT REG_FIELD_PREP(CTX_INDIRECT_CTX_OFFSET_MASK, 0xd) > + > #endif > diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c > index 35b4e8289b5f..18f247bc8865 100644 > --- a/drivers/gpu/drm/xe/xe_lrc.c > +++ b/drivers/gpu/drm/xe/xe_lrc.c > @@ -1449,15 +1449,15 @@ setup_indirect_ctx(struct xe_lrc *lrc, struct xe_hw_engine *hwe) > finish_bo(&state); > kfree(state.buffer); > > - /* > - * Enable INDIRECT_CTX leaving INDIRECT_CTX_OFFSET at its default: it > - * varies per engine class, but the default is good enough > - */ > xe_lrc_write_ctx_reg(lrc, > CTX_CS_INDIRECT_CTX, > (xe_bo_ggtt_addr(lrc->bo) + state.offset) | > /* Size in CLs. */ > (state.written * sizeof(u32) / 64)); > + if (GRAPHICS_VER(lrc_to_xe(lrc)) < 20) > + xe_lrc_write_ctx_reg(lrc, > + CTX_CS_INDIRECT_CTX_OFFSET, > + CTX_INDIRECT_CTX_OFFSET_DEFAULT); > > return 0; > } > -- > 2.54.0 > -- Matt Roper Graphics Software Engineer Linux GPU Platform Enablement Intel Corporation