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As discussed with Bryan, this series shares our independent implementation so the approaches can be compared. Two aspects covered here are not in [1]: - Settle count calculation derived from sensor-reported T_PREPARE and T_PREAMBLE timing via get_mbus_config(). [1] left this as an open question. - Data rate based register sequence selection using effective bit rate (link_freq * 32 / 7). [1] noted downstream does this but deferred it; this series implements it. MIPI CSI-2 operates over two physical layer variants. D-PHY uses a dedicated differential clock lane with up to four data lanes. C-PHY encodes the clock within the data stream across up to three wire trios, eliminating the dedicated clock lane. Patch 1 extends the generic PHY framework with PHY_MODE_MIPI_CPHY and struct phy_configure_opts_mipi_cphy. Patch 2 adds t_prepare_ns and t_preamble_ns fields to the CSI-2 media bus configuration and extends CAMSS to forward them to the PHY provider for settle count calculation. Sensor drivers must implement get_mbus_config() and return non-zero values in nanoseconds; stream-on returns -EINVAL otherwise. The strictness is deliberate: C-PHY settle timing is symbol-rate-range specific and no safe value can be derived from link frequency alone. A conservative fallback could be added if reviewers prefer. Patches 3-6 extend the Qualcomm CSIPHY driver: refactor D-PHY register storage to accommodate C-PHY, accept C-PHY mode with multiple data rate table selection, compute settle count, and add lane power mask support for C-PHY trios. C-PHY encodes 16 bits per 7 symbols, so the effective bit rate is: bit_rate = link_freq * 2 * 16 / 7 = link_freq * 32 / 7 where link_freq is symbol_rate / 2 as reported by the sensor via get_mbus_config(). The rate-table entry whose bandwidth first meets or exceeds bit_rate is selected. The settle count defines how many timer clock cycles the CSIPHY receiver waits before scanning for C-PHY sync. It is computed from the sensor's T_PREPARE and T_PREAMBLE timing. The /3 factor reflects that C-PHY distributes the preamble sequence across three trios: settle_cnt = (t_prepare_ns + t_preamble_ns / 3) * timer_clk_rate / 1e9 D-PHY settle count is unchanged from before this series. [1] https://lore.kernel.org/all/20261016-x1e-cphy-rfc-v3-0-40a346a72153@gmail.com/ Signed-off-by: Nihal Kumar Gupta --- Nihal Kumar Gupta (6): phy: core: Add MIPI C-PHY configurations media: qcom: camss: Add C-PHY timing fields and get config from sensor phy: qcom: mipi-csi2: Split D-PHY register settings phy: qcom: mipi-csi2: Accept C-PHY mode and add register sequence phy: qcom: mipi-csi2: Add C-PHY settle calculation phy: qcom: mipi-csi2: Add lane mask calculation for C-PHY drivers/media/platform/qcom/camss/camss-csiphy.c | 90 +++++++++--- drivers/media/platform/qcom/camss/camss-csiphy.h | 2 + drivers/media/platform/qcom/camss/camss.c | 8 +- drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c | 159 +++++++++++++++++---- drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c | 51 +++++-- drivers/phy/qualcomm/phy-qcom-mipi-csi2.h | 25 +++- include/linux/phy/phy.h | 47 ++++++ include/media/v4l2-mediabus.h | 2 + 8 files changed, 315 insertions(+), 69 deletions(-) --- base-commit: 2efb7a11f1aa4d2dc285fe2680cca22cb9f72f64 change-id: 20261017-cphy_support-2ce4d656e631 Best regards, -- Nihal Kumar Gupta