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Sat, 17 Oct 2026 10:13:49 -0700 (PDT) X-Received: by 2002:a05:693c:8092:b0:35c:ea0d:a9a6 with SMTP id 5a478bee46e88-361a2942afcmr4574696eec.32.1792257229161; Sat, 17 Oct 2026 10:13:49 -0700 (PDT) Received: from hu-nihalkum-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-360813b6e33sm17893966eec.7.2026.10.17.10.13.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Oct 2026 10:13:48 -0700 (PDT) From: Nihal Kumar Gupta Date: Sat, 17 Oct 2026 22:43:12 +0530 Subject: [PATCH RFC 5/6] phy: qcom: mipi-csi2: Add C-PHY settle calculation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261017-cphy_support-v1-5-8b0e1237ce95@oss.qualcomm.com> References: <20261017-cphy_support-v1-0-8b0e1237ce95@oss.qualcomm.com> In-Reply-To: <20261017-cphy_support-v1-0-8b0e1237ce95@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Bryan O'Donoghue , Vladimir Zapolskiy , Loic Poulain , Mauro Carvalho Chehab , Bryan O'Donoghue Cc: Vikram Sharma , linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, Nihal Kumar Gupta X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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Add a C-PHY settle count helper and select the settle calculation from the configured PHY mode. Use the sensor-provided t_prepare_ns and t_preamble_ns values to derive the C-PHY settle count: settle_cnt = (t_prepare_ns + t_preamble_ns / 3) * timer_clk_rate / NSEC_PER_SEC Signed-off-by: Nihal Kumar Gupta --- drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c | 54 ++++++++++++++++++---- 1 file changed, 44 insertions(+), 10 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c index 30f7f39ba855a0a2921189050f0084dead207fbd..d93fd9845b50bd7e5623013aecd6db42dd491dca 100644 --- a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c +++ b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c @@ -210,7 +210,7 @@ static void phy_qcom_mipi_csi2_reset(struct mipi_csi2phy_device *csi2phy) } /* - * phy_qcom_mipi_csi2_settle_cnt_calc - Calculate settle count value + * phy_qcom_dphy_settle_cnt - Calculate settle count value * * Helper function to calculate settle count value. This is * based on the CSI2 T_hs_settle parameter which in turn @@ -218,7 +218,7 @@ static void phy_qcom_mipi_csi2_reset(struct mipi_csi2phy_device *csi2phy) * * Return settle count. */ -static u8 phy_qcom_mipi_csi2_settle_cnt_calc(s64 link_freq, u32 timer_clk_rate) +static u8 phy_qcom_dphy_settle_cnt(s64 link_freq, u32 timer_clk_rate) { u32 t_hs_prepare_max_ps; u32 timer_period_ps; @@ -310,14 +310,44 @@ phy_qcom_mipi_csi2_gen2_config_lanes(struct mipi_csi2phy_device *csi2phy, return 0; } +static u8 phy_qcom_cphy_settle_cnt(struct mipi_csi2phy_stream_cfg *cfg, + u32 timer_clk_rate) +{ + u64 settle_cnt; + + settle_cnt = ((u64)cfg->t_prepare_ns + + DIV_ROUND_CLOSEST(cfg->t_preamble_ns, 3)) * timer_clk_rate; + do_div(settle_cnt, NSEC_PER_SEC); + + return settle_cnt; +} + static int phy_qcom_mipi_csi2_lanes_enable(struct mipi_csi2phy_device *csi2phy, struct mipi_csi2phy_stream_cfg *cfg) { + struct device *dev = csi2phy->dev; const struct mipi_csi2phy_device_regs *regs = csi2phy_dev_to_regs(csi2phy); struct mipi_csi2phy_lanes_cfg *lane_cfg = &cfg->lane_cfg; u8 settle_cnt; u8 val; int i, ret; + + if (cfg->link_freq <= 0) + return -EINVAL; + + switch (csi2phy->phy_mode) { + case PHY_MODE_MIPI_CPHY: + settle_cnt = phy_qcom_cphy_settle_cnt(cfg, + csi2phy->timer_clk_rate); + break; + case PHY_MODE_MIPI_DPHY: + settle_cnt = phy_qcom_dphy_settle_cnt(cfg->link_freq, + csi2phy->timer_clk_rate); + break; + default: + dev_err(dev, "Unsupported PHY mode %u\n", csi2phy->phy_mode); + return -EINVAL; + } if (!settle_cnt) return -ENODEV; @@ -334,17 +364,21 @@ static int phy_qcom_mipi_csi2_lanes_enable(struct mipi_csi2phy_device *csi2phy, writel(val, csi2phy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->common_regs_offset, 5)); - /* Lane configuration for polarity @ CSIPHY-base + CTRL9 */ - for (i = 0; i < cfg->num_data_lanes; i++) { - if (lane_cfg->data[i].pol) { - u8 pos = lane_cfg->data[i].pos; + if (csi2phy->phy_mode == PHY_MODE_MIPI_DPHY) { + /* Lane configuration for polarity @ CSIPHY-base + CTRL9 */ + for (i = 0; i < cfg->num_data_lanes; i++) { + if (lane_cfg->data[i].pol) { + u8 pos = lane_cfg->data[i].pos; - writel(BIT(2), csi2phy->base + CSIPHY_2PH_LN_CSI_2PHASE_CTRL9n(pos * 2)); + writel(BIT(2), csi2phy->base + + CSIPHY_2PH_LN_CSI_2PHASE_CTRL9n(pos * 2)); + } } - } - if (lane_cfg->clk.pol) - writel(BIT(2), csi2phy->base + CSIPHY_2PH_LN_CSI_2PHASE_CTRL9n(lane_cfg->clk.pos)); + if (lane_cfg->clk.pol) + writel(BIT(2), csi2phy->base + + CSIPHY_2PH_LN_CSI_2PHASE_CTRL9n(lane_cfg->clk.pos)); + } val = CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_COMMON_PWRDN_B; writel(val, csi2phy->base + -- 2.34.1